ECE: Electrical & Computer Engineering
Accredited by ABET
Undergraduate Programs

ECE 4520 Digital and Mixed Signal System Testing and Testable Design

Fall 2016 textbook list

The Fall 2016 ECE textbook list is available online for students.

Current Prerequisites & Course Offering

For current prerequisites for a particular course, and to view course offerings for a particular semester, see the Virginia Tech Course Timetables.

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ECE 4520 Digital and Mixed Signal System Testing and Testable Design (3C)

Various topics on testing and testable design for digital and mixed-signal systems are studied: fault modeling, logic and fault simulation, fault modeling, automatic test pattern generation, deterministic ATPG, simulation-based ATPG, delay fault testing, design for testability, built-in-self-test, and fault diagnoisis.

What is the reason for this course?

Testing has become an integrated step of digital and mixed-signal system design, and students graduating from the curriculum need to be knowledgeable of the testing and testable design processes. With increasing complexities of the designs, testing can no longer be treated as an after-thought. Without proper testing and design-for-testability, manufactured circuits and systems can incur tremendous costs in debugging and redesign. To be able to deliver high quality designs, the engineer/designer must understand the fundamental concepts behind testing and testable design, in addition to conventional circuit design knowledge. This course provides the fundamental testing concepts necessary to equip an entry-level designer/engineer to handle the testing challenges.

Program Area: Computers.

Prerequisites: 3504 and 2574.

Why are these prerequisites or corequisites required?

The prerequisites include ECE3504 and ECE2574. The students enrolled in this course should have a solid understanding of digital logic, data structures, and basic algorithms.

Department Syllabus Information:

Major Measurable Learning Objectives:
  • explain the relationship between physical failures and fault models,
  • design efficient logic and fault simulators,
  • generate test patterns using various techniques,
  • apply various design-for-testability methods, and
  • formulate diagnosis on detected faults.

Course Topics
Topic Percentage
Intro & Logic Simulation 10%
Physical Failures, Fault Models & Fault Simulation 10%
Combinational Test Pattern Generation 15%
Sequential Test Pattern Generation 10%
Delay Fault Testing 10%
Memory and Mixed-Signal Testing 10%
Design for Testability 15%
Built In Self Test 10%
Fault Diagnosis 10%

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