Composite photograph of Fred Lee and the Terascale computer system

Left: Fred Lee, Director of the Center for Power Electronics, which is working to reduce EMI noise in distributed power systems.
Right: Electromagnetic noise is a concern with large installations, such as Virginia Tech's Terascale Computing System.

The growing need for a highly reliable supply of electrical energy for critical applications, such as hospitals, telecommunications, internet, and semiconductor industry, as well as many defense and homeland security applications, is spawning the development of very complex, local power distribution systems with the massive use of power electronics converters. With more and more high-frequency switching converters being widely used, the management of the resulting electromagnetic noise is becoming a major challenge.

The current practice for reducing system interference is generally to add a filter to each converter a local, expensive, and inefficient solution. CPES has developed new technology that can eliminate the need for additional electromagnetic noise filters, resulting in considerably improved power density and simplified manufacturability of electronic power converters.

Called integrated bus filters, the technology is based on transmission line principles. The new filter is implemented as a simple, planar, low-cost, metal-ceramic sandwich structure that connects the outside power terminals with the converter inside the box. Classical filters cannot attenuate properly the noise at radio frequencies due to natural parasitic interactions with the components. The integrated planar power connection structure uses these normally harmful parasitic interactions to enhance the attenuation. Also, the attenuation at lower frequencies can be further improved by creatively utilizing interactions between the connection structure and the input power line.

Power electronics researchers have developed technology that reduces by an order of magnitude the thermally induced mechanical stresses in integrated modules for high-temperature applications.

High temperature applications incur greater thermal stress on materials as they go from environmental temperature when off, to operating temperatures. The interfaces of materials with different coefficients of thermal expansion (CTE) suffer severe stresses and can have limited lifetimes, as is the case with silicon carbide (SiC) and copper. This issue has challenged researchers at the Center for Power Electronics (CPES) as they develop integrated modules for high-temperature applications.

The new high-temperature packaging technology involves electroplating a composite layer of copper, with chromium, which has an almost-identical expansion coefficient as SiC. Chromium has high electrical resistance and is unsuitable as interconnect metal. When used in the composite layer, however, its effect on electrical resistance is negligible.

The chromium provides a buffer layer between the copper and SiC that reduces the thermal/mechanical stress by half an order of magnitude. The metallized interconnects enable a mechanically balanced structure, leading to an ultimate order-of-magnitude reduction in stressed .The technology has been implemented successfully in a two die-module and operated at 250 C.

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