For more information, visit the MicrON Group website.
ECE opened its new Micron Technology Semiconductor Processing Laboratory this fall. The Class 1,000/10,000 clean-room laboratory is the latest of the new facilities operated by Virginia Tech’s multidisciplinary Microelectronics, Optoelectronics and Nanotechnology (MicrON) Group.
The laboratory occupies 1800 square feet in Whittemore Hall and builds on a teaching laboratory that opened in 2001. New or improved capabilities include state-of-the-art photolithography, wet processing, dry etching (RIE/DRIE), chemical vapor deposition, and metallization. This gives Virginia Tech researchers on-site capabilities to produce cutting-edge prototypes for nano-structured biological and chemical sensors, organic and molecular nanoelectronics, solid-state lighting devices, microelectromechanical systems (MEMS) for sensing and communications, microfluidics for on-chip biological assays and cooling of high-power electronic circuits, and advanced chip-level packaging strategies.
The research and teaching laboratory is named for Micron Technology, in recognition of the firm’s $750,000 gift that provided the final funds that allowed the laboratory’s completion. The cleanroom joins several other of Tech’s MicrON Group facilities: a metal-organic chemical vapor depositions (MOCVD) laboratory, an electronic/optoelectronic materials laboratory, and a device characterization laboratory. An electronic packaging laboratory is also available.
Researchers in the Center for Power Electronics (CPES) have developed a “black-box” modeling approach for designing new power electronics-based electric energy distribution systems. The new method diverges from the conventional “white-box” approach, which requires detailed knowledge of the converter structure and parameters. However, the growing use of power electronics in distribution systems has made design more complicated: the size and complexity of future systems alone make white-box modeling difficult. Another complication is that converters are commercially available from numerous different vendors, who provide little or no information about the internal structure of their products.
The CPES approach is based entirely on the terminal characteristics of power converters, using a simple set of small-signal measurements to construct the low-frequency model without requiring any knowledge of the converter structure or any of its internal parameters. Called the black-box modular-terminal-behavioral modeling methodology, the model captures the information without neglecting parasitics or simplifying the converter internal operation, as is common with conventional reduced-order models. The CPES approach is modular, enabling computationally efficient analysis of all electrical phenomena in the system.
Bradley Fellow Mark Lehne is investigating new analog-to-digital conversion-circuit architectures that improve a broadband wireless transceiver’s ability to efficiently detect information in the presence of strong interference. The goal is better overall performance while allowing for higher data rates and more intelligent transceivers. In order to coexist with legacy narrow-band transceivers, high-speed analog-to-digital converters must allow the receiver to operate with sufficient fidelity to detect target signals while identifying and rejecting narrow-band interference.