Back to ECE News

2004 Annual Report

Head Letter

Chair Letter

Campus Tansformation

Beyond Imaging

Photonic Biomedicine

Cell Behavior

No-Kill Sensors

Laser Scanning

Hokie Suit

Software Design

ECE Research Update

Research News

Cognitive Radio

Network Game Theory

Hardware Middleware


High-Temp Sensor

Cell phone detector

Optical Cryptography

Shoot-Through Failures



R&D 100 Award

Electronic Noses

Distributed Generation


$1000 Elevator

Embedded Systems

Defect Tolerance

Efficiency Tools

Pervasive Networks

Video Networks

Networked Testbeds

Real-Time Solutions

2002/2003 Ph.D.s

2003 Patents




Special Report:
ECEs and Biomedicine

April 2004


For more information, visit the PROACTIVE website.

Efficiency tools for IC design, testing, verification

The PROACTIVE laboratory is developing software tools to reduce IC design, testing, and verification time, which now comprise 70 percent of design time.

Under a new grant from the NSF, the team, headed by Michael Hsiao, is developing revolutionary graph-theoretic algorithms to improve the design verification for large and complex sequential systems. They are developing novel automatic test pattern generation techniques to use where conventional binary-decision-diagram (BDD) approaches fail. Recent results show that an order of magnitude improvement in computational complexity can be achieved with the proposed approach.

Improving the testing of high-performance chips is the goal of a new contract with Intel. Higher clock rates, shrinking geometries, longer wires, and increased density make chips more vulnerable to speed-related failures. “Our research is to address global sequential testing issues on delay-related defects, with a benefit of both reducing delay test pattern size and potential yield loss.”

Privacy Statement | Contact Webmaster

© 2006 Virginia Tech Department of Electrical and Computer Engineering
Images on this site are the property of Virginia Tech.
They may not be used for commercial purposes.
Last updated: Wed, Jun 9, 2004