As electronic systems get more compact and complex, the interconnection of the components gets more difficult. Increased density raises issues such as excessive heat generated, unplanned parasitic capacitance and inductance, thermal stresses, and bonding reliability.
Dealing with the trade-offs between these electrical, mechanical, and thermal issues requires expertise in power electronics, microelectronics, mechanical engineering and materials engineering.
Single individuals do not have enough expertise in every area to be able to solve difficult integration problems alone, according to Professor G.Q. Lu, an expert in electronic materials and microelectronics packaging. "So, we work in multidisciplinary teams to determine the optimal packaging configuration for a system. You could say that the smaller we make it, the more experts we need," he said.
"For example, if the electrical engineers design a system to work at a certain high power level, the mechanical engineers would figure out ways to remove the heat generated and might say, 'Sure, we can do it if we use this cooling system with certain properties.' The materials experts could come back and say, 'we can get the properties if we combine those materials together.' Quite often, all parties have to sit down and negotiate for an optimal solution that is doable and cost effective."
Innovative High-Power Building Blocks
Integration is particularly challenging with high-power devices. Heat flows out of a circuit, heating the whole package. The attached components are made of different materials that have different coefficients of thermal expansion, causing thermal stresses. "With high-power transistors, you have to worry about high-temperature reliability," Lu said. "You need to make sure one layer keeps bonding to another through the thermal cycle. The heating and cooling then could generate fatigue and fracture problems, which impacts package reliability and long-term performance."
So, when researchers from the Virginia Power Electronics Center (VPEC) developed an innovative high-power module for the Power Electronics Building Block (PEBB) effort, they assembled a multidisciplinary packaging team. The PEBB module was designed to be an off-the-shelf universal power processor that could be used to change any electrical power input to any desired form of voltage, current and frequency output.
"Our goal on the PEBB project is to develop processors that are smaller, faster, and less expensive than current devices," said Professor Fred Lee, VPEC director. The PEBB modules need to be able to be stand-alone, or be readily connected to other modules, he explained.
With Professor Doug Nelson from mechanical engineering involved in thermal modeling, Lu heading up the materials effort, and Lee and Professor Dusan Borojevic leading the power electronics effort, the team developed a low-cost packaging approach for the PEBB modules. The concept uses direct bonding of copper posts, instead of conventional wire-bonding of fine aluminum wires, to interconnect the power devices and join the different circuit planes together.
"Our new concept is a 3-D packaging approach, as opposed to a planar, one-dimensional bond package. By bonding the circuit planes with the copper posts, we can eliminate the conductor traces that bonding wires would require, and reduce parasitic inductance and capacitance," explained Shatil Haque, a graduate researcher on the team. "The 3-D packaging approach gives us volumetric efficiency so we can pack more into a smaller space," he said.
Another advantage of the new approach is that the copper post introduces an additional thermal dissipation path through the top of the module, which doubles the area for heat sinking, and reduces the overall package resistance.
The approach, called metal posts interconnected parallel plate structure (MPIPPS), has been successfully tested at power levels over 6 kW. A three-year $1.3 million research program, sponsored by the Office of Naval Research, is underway to enhance the packaging program for higher power applications.
Power Electronics Packaging Laboratory
According to the participants, the work was made possible by the Department's new Power Electronics Packaging Laboratory, which is fully equipped for the fabrication of integrated packages that interconnect power semiconductor devices, power integrated circuits, sensors, and protection circuits.
The laboratory sports a permanent class 1000 clean enclosure, with a clean oven, plasma cleaner, spin coater, and chemical wet station for polymer and hybrid circuit processing. Complete ceramic processing is also available with a diamond saw, industrial laser, drying and firing ovens, and a lamination press. Die-attach equipment, a wire bonder, electrical miniaturization pre-station and electrode deposition areas enable researchers to build and test prototype packages.
The laboratory was built in 1997 to bring together interdisciplinary work that until then was performed in facilities scattered across the campus. "Having the capability in one place to perform the many tasks involved in integrated packaging has made it possible for us to work as a team and concentrate on developing innovative technologies," Lu said.