Hardware/Software Codesign Environment:
GEZEL is a cycle-based hardware description language based on the
Finite-State-Machine + Datapath (FSMD) model. The GEZEL tools offer
stand-alone simulation, cosimulation, and code-generation into
synthesizable (VHDL) code. Through user-defined library-block
extensions in C++, new cosimulation interfaces can be added. GEZEL is
Hardware/Software Codesign with DE2i-150:
We are integrating the DE2i-150 board in the computer engineering
curriculum as part of the ECE 4530 course, "Hardware/Software Codesign".
The project website collects design examples and instructional materials.
This project is supported by the Intel Embedded University Program.
Performance Evaluation of SHA-3 Candidates:
The work of performance evaluation of SHA-3 candidates in ASIC and
FPGA is part of the NIST sponsored project, "Environment for Fair and
Comprehensive Performance Evaluation of Cryptographic Hardware and
Software". This webpage list all the publications, source codes and
scripts related to the SHA-3 hardware benchmarking work completed at
Physical Unclonable Functions at SES:
We are focusing on a comprehensive approach to build an efficient,
practically usable PUF. We work in architecture design as well as high
level algorithmic/statistical techniques. We have collected on-chip
variability data of nearly 200 state-of-the-art ICs, designed
functional prototypes of PUFs, analyzed aging effects, and created
improved entropy extraction methods.
IA-Meter: Toolkit for Implementation Attack Evaluation:
We're developing a modular testing environment for use in verifying
the implementation attack resistance of secure systems. The proposed
environment is an open-source solution for implementation attack
testing, independent of the system platform. We aim to support the
development of an implementation attack security standard in which
standard test procedures are published openly and used to evaluate
Open-source ECDLP Cryptanalytic Engine in Bluespec:
We developed a hardware solver for the Elliptic Curve
Discrete Logarithm (ECDLP) problem in Bluespec, for the curve
secp112r1. This implementation has been demonstrated on a Nallatech
FSB-Compute platform with Virtex-5 LX-330 FPGA. The measured
performance of the resulting design is 114 cycles per Pollard rho step
at 100 MHz, which gives 878 K iterations per second per ECC core.
SUNSHINE: A Software-Hardware Emulator for Sensor Networks:
SUNSHINE (Sensor Unified aNalyzer for Software and Hardware in
Networked Environments) supports hardware-software co-design in
sensornets. By the integration of a network simulator TOSSIM, an
instruction-set simulator SimulAVR, and a hardware simulator GEZEL,
SUNSHINE can simulate the impact of various hardware designs on
sensornets at cycle-level accuracy. The performance of software
network protocols and applications under realistic hardware
constraints and network settings can be captured by SUNSHINE.