This is the course outline for the Spring 2008 version of Digital Design II.
Lecture 1: Introduction (Slides)
- Structural and Behavioral Modeling
- Top-down and Bottom-up Design
- 4-bit counter example and simulation in Modelsim
Lecture 2: Hierarchical Design (Slides)
- Structural and Behavioral Modeling
- Top-down and Bottom-up Design
- 4-bit counter example and simulation in Modelsim
Lecture 3: Verilog Bread and Butter (Slides)
- Verilog for Synthesis and Simulation
- Verilog Module Structure: Port List, Behavioral/Dataflow/Structural constructs
- Verilog Data Types, Values and Constants
Lecture 4: Gate Level Modeling (Slides)
- Structural Modeling with gate-level primitives
- Delay modeling at gate level
- Examples: Bit and Byte Comparator, Latches and Flip Flops
Lecture 5: How the Verilog Simulator Workds (Slides)
- Structure and operation of an event-driven simulator
- Simulation of gate networks with an event-driven simulator
- Simulation of behavioral code with an event-driven simulator
Lecture 6: Random Number Generators (Slides)
- True RNG and Pseudo RNG
- Fibonacci and Galois LFSR
- Flaws in RNG: bias, predictability
- Non-linear combination generators
Lecture 7: Dataflow Modeling (Slides)
- Use of assign statement, formation of operands using bit-select and part-select
- Delay in dataflow assignment
- Verilog operators, expressions, precision in expressions
Lecture 8: Multiplexed Datapaths (Slides)
- Multiplexed datapaths can be made using registers and assign statements
- Rules: use single-clock, use edge-triggered flipflops, use register-at-the-output
- Through multiplexed datapaths, we can trade-off area and time for different solutions
- Finite State Machines can be modeled using the same approach
Lecture 9: System Commands and Testbenches (Slides)
- System commands for display and file I/O
- VCD Files, format and usage
Lecture 10: Behavioral Modeling: Non-blocking Assignments (Slides)
- Non-blocking assignments split RHS evaluation from LHS assignment
- Used to model registers in always blocks
- VCD Files
Lecture 11: Design of a SHA-1 Module in Verilog (Slides)
- SHA-1 = Secure Hashing Algorithm
- Illustration of non-blocking assignment (<=) and register-transfer level design
Lecture 12: Behavioral Modeling/ Conditionals and Loops (Slides)
- Elements of Behavioral Modeling
- if-the-else, case
- loops
- parallel block, named block
- Generate statement
Lecture 13: Logic Synthesis (Slides)
- Hardware Inference: The rules that govern Verilog to hardware translation
- How to capture combinational logic in an always block
- How to capture registers in an always block
- How to recognize warnings and errors from the tools when you synthesize your design
Lecture 14: Spartan 3ES500 FPGA (Slides)
- Implementation details of FPGA: CLB's and the interconnection network
- Analysis of data sheet table, tool diagnostic output
Lecture 15: FSM-based Control (Slides)
- Verilog mapping for synthesizable FSM
- State encoding using synthesis tools
- Synthesis issues: default state assignment, safe FSM, RAM-based FSM
- FSM-based control of datapath
Lecture 16: Synthesis of Memories in FPGA (Slides)
- Design flow for Memory Elements
- Inference and instantiation
- Integrated synthesis and simulation
- Memory Elements
- Register Files
- Memory Arrays: SRAM and DRAM
- Operation of SRAM and DRAM
- SRAM in Spartan 3E FPGA
Lecture 17: Hardware Division (Slides)
- Division as an 'inverted' multiplication
- Division one digit at-a-time: digit-recurrence
- The restoring divider algorithm
- The non-restoring divider algorithm
- Designing an architecture for a non-restoring divider
Lecture 18: Optimizing Area (Slides)
- Area and Performance Constraints in digital design
- Area-Delay product and 'optimal' design
- Area optimization using resource sharing
- Hardware sharing factor
- Example: unshared multiplier, shared multiplier, multiplication with a constant
Lecture 19: Optimizing Performance (Slides)
- Performance factors of a digital design
- Latency and Throughput
- Delay = Clock Period * Cycle Count
- What determines the minimum clock period?
- Performance Optimizations you can do in Verilog
- Parallel Computations
- Pipelining
- Retiming
- Summary Optimizing Area & Performance
Lecture 20: Static Timing Analysis (Slides)
- Static and Dynamic Timing Analysis
- Static Timing Analysis
- Delay Model
- Path Delay
- False Paths
- Timing Constraints
- FPGA Design Flow & STA: Sorter Example
- Dynamic Timing Analysis
- FPGA Design Flow & Timed Simulation
- Delay back-annotation with SDF files
- Demonstration
Lecture 21: Functions and Tasks (Slides)
- Functions and Tasks
- Functions and Tasks enable shorthand notations within always and initial blocks
- Functions are single-output, and do not support event control
- Tasks may have more then a single output, and may have event-control statements
- In practice, only functions are used in synthesis
Lecture 22: Design Economics (Slides)
- Wows and Woes of scaling
- The case of the Microprocessor
- How efficient does a microprocessor use transistors ?
- Alternative Technologies: FPGA, ASIC, Full Custom
- Energy Efficiency and Design Cost