• Hardware/Software Codesign for Secure Embedded Systems
• Side-channel analysis and countermeasure methodologies
• Secure Debugging and Protection of Embedded Firmware
• Reliable Circuits for Uniqueness and Randomness
• Standard Interface for Hardware Hash Algorithms

Our group works on design and implementation aspects of security in embedded systems design. We work on secure embedded hardware and software required to implement secure prototocols and cryptography. Where needed, we develop appropriate countermeasures against physical attacks. Our team's expertise covers multiple abstraction levels, including circuits, hardware micro-architecture, firmware, and platform-specific software. We are also working on methodologies, with a focus on the trade-off between system performance, system cost, and system security.

We are grateful for the support of our sponsors: The National Science Foundation (Arlinton, VA), McQ Inc, and ST Micro-electronics.

Read about our activities in the 2007 ECE Department yearly report.

Hardware/Software Codesign for Secure Embedded Systems

• Hardware Coprocessors for cryptography and specialized primitives (TRNG, PUF).
• Side-channel resistant design of symmetric-key and public-key crypto in hardware and software.
• Heterogeneous and homogeneous multi-core programming for performance and security.
• Design flows and software for Hardware/Software Codesign

Recent Publications

• X. Guo, P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage", Design, Automation and Test in Europe (DATE2009), April 2009.
• X. Guo, P. Schaumont, "Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA based SoC Platform", 5th International Workshop on Applied Reconfigurable Computing (ARC2009), LNCS5453, pp. 169-180, Springer Verlag, March 2009.
• X. Guo, Z. Chen, P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
• P. Schaumont, E. Simpson, P. Yu, "A Video Interface with End-point Security," Technical Report, ECE Department, Virginia Tech, January 2008.

Software

• The GEZEL Design Environment

Side-channel analysis and countermeasure methodologies

• Analysis of circuit-level countermeasures based on hiding and masking.
• Analysis of software-level countermeasures based on hiding and masking.

Recent Publications

• Z. Chen, P. Schaumont, "Improving Secure Hardware Masking using an Equalization Technique", ACM Workshop on Embedded Systems Security (WESS 2008), October 2008.
• Z. Chen, X. Guo, R. Nagesh, A. Reddy, M. Gora, and A. Maiti, "Hardware Trojan Designs on BASYS FPGA Board," Embedded System Challenge Contest in Cyber Security Awareness Week (CSAW08) (Technical Report), 2008.
• Z. Chen, P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme", IEEE International Workshop on Hardware-Oriented Security and Trust, June 2008.
• P. Yu, "Implementation of DPA-Resistant Circuit for FPGA," Master's thesis, Virginia Tech, 2007. [PDF].
• P. Yu, P. Schaumont, "Secure FPGA Circuits using Controlled Placement and Routing," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), October 2007.
• P. Schaumont, K. Tiri, "Masking and Dual-Rail Logic Don't Add Up," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), September 2007.

Secure Debugging and Protection of Embedded Firmware

• Remote authentication of embedded system platforms.
• Firmware protection and encryption for embedded systems.
• Secure debugging interfaces and Authenticated JTAG.

Recent Publications

• M. Gora, E. Simpson, P. Schaumont, "Intellectual Property Protection for Embedded Sensor Nodes," International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
• Eric Simpson, "Runtime Intellectual Property Protection on Programmable Platforms," Master's thesis, Virginia Tech, 2007. [PDF].
• E. Simpson, P. Schaumont, "Offline HW/SW Authentication for Reconfigurable Platforms," Workshop on Cryptographic Hardware and Embedded Systems 2006 (CHES 06), Yokohama, Japan, October 2006.

Reliable Circuits for Uniqueness and Randomness

• Physical Unclonable Functions (PUF) in Field-Programmable Gate Array.
• True Random Number Generation (TRNG) in Field-Programmable Gate Array.
• Evaluation and Testing of PUF/TRNG for Field-Programmable Gate Array.

Recent Publications

• A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Compact and Scalable PUF-TRNG,", 19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009.
• A. Maiti, P. Schaumont, "Impact and Compensation of Correlated Process Variations on Ring Oscillator Based PUF," poster presentation, 17th International Symposium on Field Programmable Gate Arrays (FPGA 2009), February 2009.
• P. Schaumont, D. Hwang, "Turning Liabilities into Assets: Exploiting Deep-submicron CMOS Technology to Design Secure Embedded Circuits," IEEE International Symposium on Circuits and Systems (ISCAS 08), May 2008, Seattle.

Standard Interface for Hardware Hash Algorithms

• Standard hardware performance-evaluation of SHA-3 candidates.
• Standard testbench and interfaces for SHA-3 candidates.

Recent Publications

• Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms", ePrint IACR Archive, 2008/529, December 2008.