Secure Embedded Systems
Virginia Tech

• Side-channel analysis and countermeasure methodologies
• Intellectual Property Protection of Embedded Firmware
• Hardware/Software Codesign for Secure Embedded Systems

The Secure Embedded Systems Group investigates the design and implementation aspects of security in embedded-systems. We work on secure embedded hardware design, secure embedded software design, and the interface between the two. We also develop systematic design methods for such systems. We investigate implementations with maximal energy-efficiency and selected side-channel resistance. Our lab has a collection of embedded-processor-based and FPGA-based prototyping platforms to complement research concepts with working implementations.

Read about our activities in the 2007 ECE Department yearly report!

• "Tree of Trust," Bradley Department of Electrical and Computer Engineering, 2007.

Below you will find summaries of our ongoing projects.

Side-channel analysis and countermeasure methodologies

Side-channel Analysis Setup

Related publications on side-channel analysis:

• Z. Chen, P. Schaumont, "Slicing Up a Perfect Hardware Masking Scheme," IEEE Workshop on Hardware Oriented Security and Trust, May 2008.
• P. Schaumont, K. Tiri, "Masking and Dual-Rail Logic Don't Add Up," Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), September 2007.
• K. Tiri, P. Schaumont, "Changing the odds against masked logic," 13th Annual Workshop on Selected Areas in Cryptography, Montreal, Canada, 2006.

We are also working on countermeasure methodologies against known side-channel analysis techniques. We have developed several FPGA-specific design techniques for such circuits. Relevant publications include

• P. Yu, P. Schaumont, "Secure FPGA Circuits using Controlled Placement and Routing," International Conference on Hardware/Software Codesign and System Synthesis, October 2007.
• P. Yu, "Implementation of DPA-Resistant Circuits for FPGA," MS Thesis, Virginia Tech, 2007.

Intellectual Property Protection of Embedded Firmware

Current embedded systems contain large amounts of intellectual property in the form of embedded software and hardware configurations, for components including embedded processors, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA). We are developing mechanisms to protect the intellectual property of this firmware at runtime.

Design Flow for DSP Firmware Protection

Relevant Publications include

• M. Gora, E. Simpson, P. Schaumont, "Intellectual Property Protection for Embedded Sensor Nodes," International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
• E. Simpson, P. Schaumont, "Offline HW/SW Authentication for Reconfigurable Platforms," Workshop on Cryptographic Hardware and Embedded Systems 2006 (CHES 06), Yokohama, Japan, October 2006.
• E. Simpson, "Runtime Intellectual Property Protection on Programmable Platforms", MS Thesis, Virginia Tech, 2007.

Hardware/Software Codesign for Secure Embedded Systems

We are developing a hardware-software codesign environment with specific support for secure embedded system design. The objective of secure embedded system design is to protect the root-of-trust from being compromised. The activities in this project include the partitioning of systems into secure and non-secure parts, and the development of secure interfaces to integrate those partitions back into a single system.

The SAM prototype (Secure VGA Display Peripheral).

Relevant Publications include

• X. Guo, Z. Chen, P. Schaumont, "Energy and Performance Evaluation of an FPGA-based SoC Platform with AES and PRESENT Coprocessors", International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
• P. Schaumont, E. Simpson, P. Yu, "A Video Interface with End-point Security,", Technical Report, ECE Department, Virginia Tech, January 2008
• P. Schaumont, "A senior-level course in hardware-software codesign," International Conference on Microelectronic Systems Education (MSE 2007), San Diego, June 2007.

• P. Schaumont, D. Hwang, "Turning Liabilities into Assets: Exploiting Deep-submicron CMOS Technology to Design Secure Embedded Circuits,", IEEE International Symposium on Circuits and Systems (ISCAS 08), May 2008, Seattle