| [PDF] |
S. Morozov, A. Maiti, P. Schaumont, "A Comparative Analysis
of Delay Based PUF Implementations on FPGA," IACR ePrint
Archive 2009/629, December 2009.
|
| [PDF] |
X. Guo, J. Fan, P. Schaumont, I. Verbauwhede,
"Programmable and Parallel ECC Coprocessor Architecture:
Tradeoffs between Area, Speed and Security,,"Proc. of the
IACR Workshop on Cryptographic Hardware and Embedded Systems
(CHES 2009), September 2009.
|
| [PDF] |
A. Maiti, P. Schaumont, "Improving the Quality of a
Physical Unclonable Function using Configurable Ring
Oscillators," 19th International Conference on Field
Programmable Logic and Applications (FPL 2009), September 2009.
|
| [PDF] |
Z. Chen, P. Schaumont, "Early Feedback on Side-Channel
Risks with Accelerated Toggle-Counting," Proc. IEEE Workshop
on Hardware Oriented Security and Trust (HOST 2009), July
2009.
|
| [PDF] |
M. Gora, A. Maiti, P. Schaumont, "A Flexible Design Flow
for Software IP Binding in Commodity FPGA," IEEE Symposium
on Industrial Embedded Systems (SIES 2009), July 2009.
|
| [PDF] |
Z. Chen, P. Schaumont, "Side-channel Leakage in Masked
Circuits Caused by Higher-Order Circuit Effects," 3th
International Conference on Information Security and Assurance
(ISA 2009), June 2009.
|
| [PDF] |
Z. Chen, R. Nagesh, A. Reddy, P. Schaumont, "Increasing the
Sensitivity of On-Chip Digital Thermal Sensors with
Pre-Filtering," IEEE Computer Society Annual Symposium on
VLSI (ISVLSI 2009), May 2009.
|
| [PDF] |
A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical
Unclonable Function and True Random Number Generator: a Compact
and Scalable Implementation," 19th Great Lakes Symposium on
VLSI (GLSVLSI 2009), May 2009.
|
| [PDF] |
X. Guo,
P. Schaumont, "Optimizing the HW/SW Boundary of an ECC SoC
Design Using Control Hierarchy and Distributed Storage," Design,
Automation and Test in Europe (DATE2009), April 2009.
|
| P.
Schaumont, A.K. Jones, S. Trimberger, "Guest Editors' Introduction
to Security in Reconfigurable Systems Design," ACM
Transactions on Reconfigurable Technology and Systems (TRETS),
March 2009.
|
| [PDF] | X. Guo,
P. Schaumont, "Optimizing the Control Hierarchy of an ECC
Coprocessor Design on an FPGA based SoC Platform," 5th
International Workshop on Applied Reconfigurable Computing
(ARC2009), LNCS5453, pp. 169-180, Springer Verlag, March 2009.
|
| A. Maiti,
P. Schaumont, "Impact and Compensation of Correlated Process
Variations on Ring Oscillator Based PUF," poster
presentation, 17th International Symposium on Field Programmable
Gate Arrays (FPGA 2009), February 2009.
|
| [PDF] |
Z. Chen, S. Morozov, P. Schaumont, "A Hardware Interface for Hashing Algorithms",
ePrint IACR Archive, 2008/529, December 2008.
|
| [PDF] |
P. Schaumont, "Hardware/Software Codesign is a Starting Point in Embedded Systems Architecture Education",ARTIST Workshop on Embedded Systems Education (WESE 2008), October 2008
|
| [PDF] |
Z. Chen, P. Schaumont, "Improving Secure Hardware Masking using an Equalization Technique",
ACM Workshop on Embedded Systems Security (WESS 2008), October 2008.
|
| [PDF] | X. Guo,
Z. Chen, P. Schaumont, "Energy and Performance Evaluation of an
FPGA-based SoC Platform with AES and PRESENT Coprocessors",
International Workshop on Systems, Architectures, Modeling, and
Simulation (SAMOS 2008), July 2008.
|
| [PDF] | M. Gora,
E. Simpson, P. Schaumont, "Intellectual Property Protection for
Embedded Sensor Nodes," International Workshop on Systems,
Architectures, Modeling, and Simulation (SAMOS 2008), July 2008.
|
| [PDF] | Z. Chen,
P. Schaumont, "Slicing Up a Perfect Hardware Masking
Scheme", IEEE International Workshop on Hardware-Oriented
Security and Trust, June 2008.
|
| [PDF] |
P. Schaumont, K. Asanovic, J. Hoe, "MEMOCODE 2008 Co-Design
Contest", Sixth ACM-IEEE International Conference on Formal
Methods and Models for Codesign (MEMOCODE'2008), June 2008.
|
| [PDF] |
P. Schaumont, E. Simpson, P. Yu, "A Video Interface with
End-point Security,", Technical Report, ECE Department,
Virginia Tech, January 2008.
|
| [PDF] |
P. Schaumont, D. Hwang, "Turning Liabilities into
Assets: Exploiting Deep-submicron CMOS Technology to Design
Secure Embedded Circuits,", IEEE International Symposium on
Circuits and Systems (ISCAS 08), May 2008,
Seattle..
|
| [PDF] |
P. Schaumont, "A Senior Level Course in
Hardware/Software Codesign," IEEE Transactions on Education,
Special Issue on Micro-Electronic Systems Education,
51(3):306-311, August 2008.
|
| [PDF] |
P. Schaumont, A. Raghunathan,
"Guest Editor's Introduction: Security and Trust in Embedded-Systems Design,"
IEEE Design and Test of Computers, Special Issue on Design and Test
of ICs for Secure Embedded Computing, November/December 2007.
|
| [PDF] |
P. Yu, P. Schaumont,
"Secure FPGA Circuits using Controlled Placement and
Routing," International Conference on Hardware/Software
Codesign and System Synthesis (CODES+ISSS 2007), October
2007.
|
| [PDF] |
P. Schaumont, K. Tiri,
"Masking and Dual-Rail Logic Don't Add Up," Workshop on
Cryptographic Hardware and Embedded Systems (CHES 2007),
September 2007.
|
| [PDF] |
E. Simpson, P. Yu, P. Schaumont, S. Ahuja, S. Shukla,
"VT Matrix Multiply Design for MEMOCODE 07," Fifth
ACM-IEEE International Conference on Formal Methods and Models
for Codesign (MEMOCODE'2007), Nice, France.
|
[PDF]
[PPT] |
P. Schaumont,
"A Senior Level course in hardware-software codesign,"
International Conference on Microelectronic Systems Education
(MSE 2007), San Diego, June 2007.
|
[PDF]
[PPT] |
I. Verbauwhede, P. Schaumont, "Design Methods for
Security and Trust," Design Automation and Test Conference
in Europe (DATE 2007), Nice, France, April
2007.
|
| [PDF] |
D. Ha, P. Schaumont, "Replacing Cryptography with Ultra
Wideband (UWB) Modulation in Secure RFID," IEEE
International Conference on RFID 2007, Grapevine, TX, March
2007.
|
| [PDF] |
P. Schaumont, I. Verbauwhede, "Hardware/Software
Codesign for Stream Ciphers," SASC (State of the Art of
Stream Ciphers), Special workshop hosted by the ECRYPT Network
of Excellence in Cryptology, Bochum, Germany, January
2007.
|
| [PDF] |
E. Simpson, P. Schaumont, "Offline HW/SW Authentication
for Reconfigurable Platforms," Workshop on Cryptographic
Hardware and Embedded Systems 2006 (CHES 06), Yokohama, Japan,
October 2006.
|
| [PDF] |
P. Schaumont, D. Hwang, S. Yang, I. Verbauwhede,
"Multi-level Design Validation in a Secure Embedded
System," IEEE Transactions on Computers, special issue HLDVT
2005, October 2006.
|
| [PDF] |
P. Schaumont, I. Verbauwhede, "A Component-based Design
Environment for Electronic System-level Design," IEEE
Design and Test of Computers, special issue on Electronic
System-Level Design, 23(5), pp. 338-347, September-October 2006.
|
| [PDF] |
K. Tiri, P. Schaumont, "Changing the odds against masked
logic," 13th Annual Workshop on Selected Areas in
Cryptography, Montreal, Canada, 2006.
|
| [PDF] |
B.C. Lai, P. Schaumont, W. Qin, I. Verbauwhede, "Cross
Layer Design to Multi-thread a Data-Pipelining Application on a
Multi-processor on Chip," IEEE 17th INTERNATIONAL
CONFERENCE ON Application-specific Systems, Architectures and
Processors (ASAP), pp.15-18, Steamboat Springs, Colorado,
September 2006.
|
| [PDF] |
P. Yu, P. Schaumont, "Executing Hardware as Parallel Software
for Picoblaze Networks," 16th International Conference on
Field Programmable Logic and Applications (FPL 2006), Madrid,
Spain, August 2006.
|
| [PDF] |
P. Yu, P. Schaumont, D. Ha, "Securing RFID with
Ultra-Wideband Modulation," 2nd Workshop on RFID Security
(RFIDSec 2006), Graz, Austria, July 2006.
|
| [PDF]
| H. Chan, P. Schaumont, I. Verbauwhede, "Process
Isolation for Reconfigurable Hardware," 2006 International
Conference on Engineering of Reconfigurable Systems & Algorithms,
June 2006. (distinguished paper).
|
| [PDF]
| D. Ching, P. Schaumont, and I. Verbauwhede,
"Integrated modeling and generation of a reconfigurable
network-on-chip," Int. J. Embedded Systems, Vol. 1, Nos. 3/4,
2005, p. 218-227.
|
| [PDF] |
K. Tiri, P. Schaumont, I. Verbauwhede, "Side-Channel
Leakage Tolerant Architectures" third International Conference
in Information Technology: New Generations (ITNG), Las Vegas, NV,
April 2006.
|
| [PDF]
| D. Hwang, K. Tiri, A. Hodjat, B.C. Lai, S. Yang,
P. Schaumont, I. Verbauwhede, "AES-Based Security Coprocessor
IC in 0.18um CMOS with resistance to differential power analysis
side-channel attacks," IEEE Journal of Solid-State Circuits,
41(4), April 2006.
|
| [PDF] |
I. Verbauwhede, K. Tiri, D. Hwang, and P. Schaumont,
"Circuits and design techniques for secure ICs resistant to
side-channel attack," International Conference on IC Design
and Technology (ICICDT 2006).
|
| [PDF] |
D. Hwang, P. Schaumont, K. Tiri, I. Verbauwhede, "Securing
Embedded Systems," IEEE Security and Privacy Magazine,
March-April 2006.
|
| [PDF] |
P. Schaumont, S. Shukla, I. Verbauwhede, "Design with
race-free hardware semantics", 2006 Design Automation and Test
in Europe (DATE) Conference, Munich, March 2006.
|
| [PDF]
| P. Schaumont, D. Ching, I. Verbauwhede, "An
Interactive Codesign Environment for Domain-specific
Coprocessors," ACM Transactions on Design Automation of
Electronic Systems, January, 2006.
|
| [PDF] |
P. Schaumont, D. Hwang, I. Verbauwhede, "Platform-based
design for an embedded fingerprint authentication device,"
IEEE Transactions on Computer Aided Design of Integrated Circuits
and Systems, 24(12):1929-1936, December 2005.
|
| [PDF] |
D. Hwang, P. Schaumont, S. Yang, I. Verbauwhede,
"Multi-level Design Validation in a Secure Embedded System,"
Proceedings of the 2005 High Level Design and Validation
Workshop, November 2005.
|
| [PDF] |
I. Verbauwhede, P. Schaumont, "Skiing the embedded systems
mountain," ACM Transactions on Embedded Computing Systems
(Special issue on embedded systems education), August 2005.
|
| [PDF] |
B.C. Lai, P. Schaumont, I. Verbauwhede, "Energy and
Performance Analysis of Mapping Parallel Multi-threaded Tasks for
An On-Chip Multi-Processor System," IEEE International
Conference on Computer Design (ICCD 2005), October 2005.
|
| [PDF] |
B.C. Lai, P. Schaumont, I. Verbauwhede, "A Light-Weight
Cooperative Multi-threading with Hardware Supported
Thread-Management on an Embedded Multi-Processor System,"
Conference Record of the Thirty-Ninth Asilomar Conference on
Signals, Systems and Computers, 2005, p. 1647-1651.
|
| [PDF] |
S. Yang, P. Schaumont, and I. Verbauwhede, "Microcoded
Coprocessor for Embedded Secure Biometric Authentication
Systems," IEEE/ACM/IFIP International Conference on Hardware -
Software Codesign and System Synthesis(CODES+ISSS'05), Sept. 2005.
|
| [PDF] |
K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang,
P. Schaumont, and I. Verbauwhede, "Prototype IC with WDDL and
Differential Routing - DPA Resistance Assessment," Workshop
on Cryptographic Hardware and Embedded Systems (CHES 2005), August
2005.
|
| [PDF] |
P. Schaumont, S. Shukla, and I. Verbauwhede, "Extended
Abstract: A Race-free Hardware Modeling Language," Third
ACM-IEEE International Conference on Formal Methods and Models for
Codesign (MEMOCODE'2005), July 2005.
|
| [PDF] |
K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang,
P. Schaumont, and I. Verbauwhede, "AES-Based Cryptographic and
Biometric Security Coprocessor IC in 0.18-um CMOS Resistant to
Side-Channel Power Analysis Attacks," 2005 Symposia on VLSI
Technology and Circuits (VLSI SYMPOSIUM 2005), pp. 216-219, June
2005.
|
| [PDF] |
P. Schaumont, B.C. Lai, W. Qin, I. Verbauwhede,
"Cooperative multithreading on embedded multiprocessor
architectures enables energy-scalable design," Proc. 2005
Design Automation Conference (DAC 2005), June 2005.
|
| [PDF] |
K. Tiri, D. Hwang, A. Hodjat, B.C. Lai, S. Yang,
P. Schaumont, I. Verbauwhede, "A Side-Channel Leakage Free
Coprocessor IC in .18um CMOS for Embedded AES-Based Cryptographic
and Biometric Processing," Proc. 2005 Design Automation
Conference (DAC 2005), June 2005.
|
| [PDF] |
O. Villa, P. Schaumont, I. Verbauwhede, M. Monchiero,
G. Palermo, "Fast dynamic memory integration in co-simulation
frameworks for multiprocessor system on-chip," Proc. Design
Automation and Test Conference in Europe (DATE 2005), pp. 804-805,
March 2005.
|
| [PDF] |
H. Chan, P. Schaumont, I. Verbauwhede, "A secure
multithreaded coprocessor interface," 3th Workshop on
Optimizations for DSP and Embedded Systems, March 2005.
|
| [PDF]
| B.C. Lai, P. Schaumont, and I. Verbauwhede,
"CT-Bus: A heterogeneous CDMA/TDMA bus for future SOC,"
Proc. 38th Asilomar Conference on Signals, Systems, and
Computers, November 2004.
|
| [PDF]
| Y. Matsuoka, P. Schaumont, K. Tiri, and
I. Verbauwhede, "Java cryptography on KVM and its
performance and security optimization using HW/SW co-design
techniques," Proc. Int. Conference on Compilers,
Architecture, and Synthesis for Embedded Systems (CASES 2004),
pp. 303-311, September 2004.
|
| [PDF]
| I. Verbauwhede, P. Schaumont, "The Happy
Marriage of Architecture And Application in next-generation
Reconfigurable Systems," ACM Computing Frontiers 2004,
April 2004.
|
| .[PDF]
| P. Schaumont, K. Sakiyama, A. Hodjat,
I. Verbauwhede, "Embedded software integration for
coarse-grain reconfigurable architectures," 2004
Reconfigurable Architectures Workshop (RAW 2004), April 2004
[ERRATUM]
|
| [PDF]
| D. Ching, P. Schaumont, I. Verbauwhede,
"Integrated Modeling and Generation of A Reconfigurable
Network-On-Chip," 2004 Reconfigurable Architectures
Workshop (RAW 2004), April 2004.
|
| [PDF]
| A. Hodjat, P. Schaumont, I. Verbauwhede,
"Architectural design features of a programmable high
throughput AES coprocessor," IEEE International Conference
on Information Technology (ITCC 2004), April 2004.
|
[PDF]
[PPT]
| I. Verbauwhede, C. Piguet, P. Schaumont,
B. Kienhuis, "Architectures and Design Techniques for
Energy Efficient Embedded DSP and Multimedia," 2004
Design Automation and Test in Europe (DATE 2004), February
2004.
|
| [PDF]
| P. Schaumont, I. Verbauwhede, "Interactive
cosimulation with partial evaluation," 2004 Design
Automation and Test in Europe (DATE 2004), February 2004.
|
| [PDF] |
P. Schaumont, I. Verbauwhede, "Domain-specific co-design
for embedded security," IEEE Computer, April 2003.
|
| [PDF] |
I. Verbauwhede, P. Schaumont, H. Kuo "Design and
performance testing of a 2.29 Gb/s Rijndael Processor," IEEE
Journal of Solid-State Circuits, pp. 569-572, March 2003.
|
| [PDF] |
P. Schaumont, I. Verbauwhede, "ThumbPod puts security
under your Thumb," Xilinx Xcell Online, Winter 2003.
|
| [PDF] |
P. Schaumont, K. Sakiyama, Y. Fan, D. Hwang, B. Lai,
A. Hodjat, S. Yang, I. Verbauwhede, "Testing ThumbPod: softcore
bugs are hard to find," IEEE International High Level Design
Validation and Test Workshop (HLDVT), November 2003.
|
| [PDF] |
D. Hwang, P. Schaumont, Y. Fan, A. Hodjat, B.C. Lai,
K. Sakiyama, S. Yang, I. Verbauwhede, "Design flow for HW / SW
acceleration transparency in the ThumbPod secure embedded
system," 2003 Design Automation Conference, pp. 60-65, Los
Angeles, June 2003.
|
| [PDF] |
K. Sakiyama, P. Schaumont, D. Hwang, I. Verbauwhede,
"Teaching trade-offs in system-level design methodologies,"
Proc. International COnference on Microelectronic Systems
Education 2003 (MSE2003), pp. 64-65, June 2003.
|
| [PDF] |
K. Sakiyama, P. Schaumont, I. Verbauwhede, "Finding the
best system design flow for a high-speed JPEG encoder," Asia
and South Pacific Design Automation Conference (ASP-DAC 2003), pp.
577-578, KitakYushu, Japan, January 2003.
|
| [PDF]
| P. Schaumont, I. Verbauwhede, "Domain-specific
tools and methods for application in security processor
design," Kluwer Journal for Design Automation of Embedded
Systems, pp. 365-383, November 2002.
|
| [PDF]
| Y. Ha, S. Vernalde, P. Schaumont, M. Engels,
R. Lauwereins, H. De Man, "Building a Virtual Framework for
Networked Reconfigurable Hardware and Software Objects,"
Journal of Supercomputing Vol. 21, No.2, pp.131-144, February
2002.
|
| [PDF]
| P. Schaumont, H. Kuo, I. Verbauwhede, "Unlocking
the design secrets of a 2.29 Gb/s Rijndael encryption
processor," 39th Design Automation Conference (DAC 2002),
pp. 634-639, New Orleans, June 2002. Student Design Contest
Winner, 1st place, operational category.
|
| [PDF]
| H. Kuo, P. Schaumont, I. Verbauwhede, "A 2.29
Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a
1.8 V, 0.18 um CMOS technology.," 2002 IEEE Custom
Integrated Circuits Conference (CICC), pp. 302-309, Orlando,
May 2002.
|
| [PDF]
| D. Desmet , P. Avasare , P. Coene , S. Decneut ,
F. Hendrickx , T. Marescaux , J. Mignolet , R. Pasko ,
P. Schaumont , D. Verkest "Design of Cam-E-leon, a Run-Time
Reconfigurable Web Camera," Embedded Processor Design
Challenges : Systems, Architectures, Modeling, and Simulation
- SAMOS, Lecture Notes on Computing Science (LNCS) 2268, April
2002.
|
| [PDF]
| R. Pasko, S. Vernalde, P. Schaumont, "Techniques
to evolve a C++ based system design language," Design,
Automation and Test in Europe Conference and Exhibition (DATE
2002), pp. 302-309, March 2002.
|
| [PDF] |
R. Pasko, L. Rynders, P. Schaumont, S. Vernalde,
D. Durackova, "High Performance Flexible All-Digital Quadrature
Up- and Down Converter Chip," IEEE Journal of Solid State
Circuits, pp. 408-416, March 2001.
|
| [PDF] |
D. Verkest, P. Avasare, P. Coene, S. Decneut, D. Desmet,
F. Hendrickx, T. Marescaux, J. Mignolet, P. Schaumont, R. Pasko,
"Design of a Secure, Intelligent, and Reconfigurable Web Cam
using a C Based System Design Flow," Asilomar 2001 Conference
on Signals, Systems and Computers, pp. 463-467, Pacific Grove, CA,
November 2001.
|
| [PDF] |
P. Schaumont, I. Verbauwhede "A reconfiguration hierarchy for
elliptic curve cryptography," Thirty-Fifth Asilomar Conference on
Signals, Systems and Computers, pp. 449-453, Pacific Grove, November
2001.
|
| [PDF] |
F. Doucet, R. Gupta, M. Otsuka, P. Schaumont, S. Shukla,
"Interoperability as a design issue in C++ based modeling
environments," 14th International Symposium on System
Synthesis, 2001, pp. 87-92, October 2001.
|
| [PDF] |
Y. Ha, S. Vernalde, P. Schaumont, M. Engels, H. De Man,
"Building a Virtual Framework for Networked Reconfigurable
Hardware and Software Objects," International Conference on
Parallel and Distributed Processing Techniques and Applications
2001 (PDPTA 2001), Las Vegas, June 2001.
|
| [PDF] |
P. Schaumont, I. Verbauwhede, K. Keutzer, M. Sarrafzadeh, "A
quick safari through the reconfiguration jungle," 38th Design
Automation Conference (DAC 2001), pp. 172-177, Las Vegas, June 2001.
|
| [PDF] |
R. Cmar, R. Pasko, J.-Y. Mignolet, G. Vanmeerbeeck,
P. Schaumont, S. Vernalde, "Platform design approach for
re-configurable network appliances," Custom Integrated
Circuits, pp. 79-82, Orlando, May 2001.
|
| [PDF] |
D. Verkest, W. Eberle, P. Schaumont, B. Gyselinckx, S. Vernalde
"C++ based system design of a 72 Mb/s OFDM transceiver for
wireless LAN," Custom Integrated Circuits Conference (CICC
2001), pp. 433-439, May 2001.
|
| [PDF] |
G. Vanmeerbeeck, P. Schaumont, S. Vernalde, M. Engels,
I. Bolsens, "Hardware/software partitioning of embedded
system in OCAPI-xl," Proceedings of the Ninth International
Symposium on Codesign (CODES), pp. 30-35, April 2001.
|
| [PDF] |
Y. Ha, B. Mei, P. Schaumont, S. Vernalde, R. Lauwereins,
H. De Man, "Development of a Design Framework for
Platform-Independent Networked Reconfiguration of Software and
Hardware," Proc. Field-Programmable Logic Conference 2001
(FPL 2001), pp. 264-274, Belfast, UK.
|
| [PDF] |
Y. Ha, P. Schaumont, S. Vernalde, R. Lauwereins, H. De Man,
"SW/HW Interface API for Java/FPGA Co-designed Applets,"
Proc. Field-Programmable Customg Computing Machines 2001 (FCCM
2001),
|
| [PDF] |
Y. Ha, G. Vanmeerbeeck, P. Schaumont, S. Vernalde,
M. Engels, H. De Man, "Virtual Java/FPGA Interface for
Networked Reconfiguration," Proc. ASP-DAC, pp. 558-563,
Japan, January 2001.
|
| [PDF]
| L. Rynders, P. Schaumont, S. Vernalde, I. Bolsens,
"High level analysis of clock regions in a C++ system
description," IEICE Transactions on Fundamentals of
Electronics Communications and Computer Sciences, December
2000, VE83A(N12):2631-2632
|
| [PDF]
| R. Pasko, R. Cmar, P. Schaumont, S. Vernalde,
"Functional Verification of an Embedded Network Component
by Co-Simulation with a Real Network," Proc. IEEE
International High Level Design Validation and Test Workshop
(HLDVT00), pp. 64-67, Berkeley, CA, USA, November 2000.
|
| [PDF] |
B. Mei, P. Schaumont, S. Vernalde, "A
Hardware-Software Partitioning and Scheduling Algorithm for
Dynamically Reconfigurable Embedded Systems,"
Proc. PRORISC Workshop, Veldhoven, The Netherlands, November
2000.
|
| |
P. Schaumont, M. Sheeran, S. Singh, A. Jantsch, "Object
Oriented Approach vs Functional Approach in System
Design," Invited Session, Proc. Forum on Design Languages
(FDL00), Tubingen, Germany, September 2000.
|
| [PDF] |
Y. Ha, P. Schaumont, M. Engels, S. Vernalde,
F. Potargent, L. Rijnders, H. De Man, "A Hardware Virtual
Machine to Support Networked Reconfiguration," Proc. IEEE
International Workshop on Rapid System Prototyping (RSP00),
p. 194-9, Paris, France, June 2000.
|
| [PDF] |
R. Pasko, L. Rijnders, P. Schaumont, S. Vernalde,
D. Durackova, "High Performance Flexible All-Digital
Quadrature Up- and Down Converter Chip," Proc. IEEE Custom
Integrated Circuits Conference (CICC00), pp. 43-46, Orlando,
FL, USA, May 2000.
|
| |
L. Rijnders, P. Schaumont, S. Vernalde, "High Level Clock
Region Design of Digital Circuits," Proc. Workshop on
Synthesis and System Integration of Mixed Technologies
(SASIMI00), Kyoto, Japan, April 2000.
|
| |
P. Schaumont, I. Bolsens, "Using C++ for Design Entry: a
Comparison based on Design Performance," User Forum
Design, Automation and Test in Europe (DATE00), Paris, France,
March 2000.
|
| [PDF] |
C. Lennard, P. Schaumont, G. de Jong, A. Haverinen,
P. Hardee, "Standards for System-level Design: Practical
Reality or Solution in Search of a Question ?," Hot Topic
Session Proc. Design, Automation and Test in Europe (DATE00),
pp. 90-96, Paris, France, March 2000.
|
| [PDF] |
Y. Ha, P. Schaumont, L. Rijnders, S. Vernalde,
F. Potargent, M. Engels, H. De Man, "A scalable
architecture to support networked reconfiguration,"
Proc. PRORISC Workshop, pp. 677-83, Mierlo, The Netherlands,
November 1999.
|
| [PDF]
| P. Schaumont, R. Cmar, S. Vernalde, M. Engels,
I. Bolsens, "Hardware Reuse at the Behavioral Level,"
Proc. Design Automation Conference (DAC99), pp. 784-789, New
Orleans, CA, USA, June 1999, Nominated Best Paper.
|
| [PDF]
| P. Schaumont, R. Cmar, S. Vernalde, M. Engels,
"A 10 Mbit/s Upstream Cable Modem with Automatic
Equalization," Proc. Design Automation Conference (DAC99),
pp. 337-340, New Orleans, LA, USA, June 1999, Design Contest
Finalist.
|
| [PDF]
| S. Vernalde, P. Schaumont, I. Bolsens, "An
Object Oriented Programming Approach for Hardware Design,"
Proc. IEEE Computer Society Workshop on VLSI, pp. 68-73,
Orlando, FL, April 1999.
|
| [PDF]
| R. Cmar, L. Rijnders, P. Schaumont, S. Vernalde,
I. Bolsens, "A Methodology and Design Environment for DSP
ASIC Fixed Point Refinement," Design, Automation and Test
in Europe (DATE99), pp. 271-276, Munich, Germany, March
1999.
|
| [PDF] |
R. Pasko, P. Schaumont, V. Derudder, S. Vernalde,
D. Durackova, "A new algorithm for Elimination of Common
Subexpressions," IEEE Transactions on Computer Aided
Design of Integrated Circuits and Systems, 18(1):58-68,
January 1999.
|
| [PDF] |
P. Schaumont, S. Vernalde, M. Engels, I. Bolsens, "Low
Power Digital Frequency Conversion Architectures," Kluwer
Journal of VLSI Signal Processing, pp. 187-197, February
1998.
|
| [PDF]
| P. Schaumont, S. Vernalde, L. Rijnders, M. Engels,
I. Bolsens, "A Programming Environment for the Design of
Complex High Speed ASICs," Proc. Design Automation
Conference (DAC98), pp. 315-320, San Francisco, CA, USA, June
1998.
|
| [PDF]
| P. Schaumont, G. Vanmeerbeeck, E. Watzeels,
S. Vernalde, M. Engels, I. Bolsens, "A Technique for
Combined Virtual Prototyping and Hardware Design,"
Proc. IEEE International Workshop on Rapid System Prototyping
(RSP98), pp. 156-161, Leuven, Belgium, June 1998.
|
| [PDF] |
P. Schaumont, B. Vanthournout, I. Bolsens, H. De Man,
"Synthesis of Pipelined DSP accelerators with Dynamic
Scheduling," IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, 5-1, pp. 59-68, March 1997.
|
| [PDF] |
R. Pasko, P. Schaumont, V. Derudder, D. Durackova,
"Optimization Method for Broadband Modem FIR Filter Design
using Common Subexpression Elimination," 10th
International Symposium on System Synthesis (ISSS97),
pp. 100-106, Antwerp, Belgium, September 1997.
|
| [PDF] |
J. Maris, P. Schaumont, S. Vernalde, M. Engels, I. Bolsens,
"Dynamical analysis of all-digital symbol timing recovery
in twisted pair broadband receivers," Digital Signal
Processing Proceedings, 1997 (DSP 97), pp. 1055-1058, July
1997.
|
| [PDF]
| P. Schaumont, S. Vernalde, M. Engels, I. Bolsens,
"Synthesis of Multi-Rate and Variable Rate Circuits for
High Speed Telecommunications Applications,"
Proc. European Design and Test Conference (EDTC97),
pp. 542-546, Paris, France, March 1997.
|
| [PDF] |
P. Vandaele, M. Moonen, P. Schaumont, W. Trog, K. De
Meyer, "Low Complexity Algorithms for Burstmode
Communication in Upstream CATV networks," Proc. PRORISC
Workshop, The Netherlands, November 1996.
|
| [PDF] |
S. Vernalde, P. Schaumont, M. Engels, I. Bolsens,
"Design Space Exploration of All-Digital Symbol Timing
Adjustment Architectures," IEEE Fourth Symposium on
Communications and Vehicular Technology in the Benelux,
pp. 88-93, Gent, Belgium, October 1996.
|
| [PDF] |
P. Schaumont, S. Vernalde, M. Engels, I. Bolsens,
"Digital Upconversion Architecture for Quadrature
Modulators," IEEE Workshop on VLSI Signal Processing,
pp. 315-324, San Francisco, CA, USA, October 1996.
|
| [PDF] |
R. Lauwereins, M. Ade, P. Vandaele, M. Moonen,
P. Schaumont, "Prototyping Quadrature Amplitude Modulation
for Two-Way Communication on CATV networks," 7th
Int. Conference on Signal Processing Applications and
Technology ICSPAT, pp. 1570-1574, Boston, MA, USA, October
1996.
|
| [PDF] |
P. Schaumont, B. Vanthournout, I. Bolsens and H. De Man,
"Synthesis of Pipelined DSP accelerators with Dynamic
Scheduling," Proc. International Symposium on System
Synthesis (ISSS95), pp. 72-77, Cannes, 1995.
|
| | D. S. Ha,
P. Schaumont, "Secure RFID Based Ultra-Wideband Time Hopped
Pulse Position Modulation," to Virginia Tech Intellectual
Properties, US Application no 11/773,734.
|
| [LNK] |
I. Verbauwhede, P. Schaumont, D. Hwang, B. Lai, S. Yang,
K. Sakiyama, Y. Fan, A. Hodjat, "System for Biometric Signal
Processing with Hardware and Software Acceleration," to
University of California, US Provisional Application no 60/475,242
(June 2, 2003).
|
| [PDF] |
P. Schaumont, S. Vernalde, J. Cox, "A design environment
and a method for generating an implementable description of a
digital system," to IMEC vzw, Belgium.
US Patent
7,006,960; 6,233,540; 6,606,588.
Japan Patent 11003367.
Europe Patent 0867820A3.
|
| [PDF] |
P. Schaumont, R. Cmar, S. Vernalde, "Reuse of Hardware
Components," to IMEC vzw, Belgium.
US Patent
7,113,901.
Europe Patent EP0991000.
|
| [PDF] |
Y. Ha, P. Schaumont, M. Engels, S. Vernalde, "Virtual
Hardware Machine Methods and Devices," to IMEC vzw.,
Belgium.
US Patent 7,150,011.
Europe Patent
1168168A2.
|
| [PDF] |
P. Schaumont, S. Vernalde, M. Engels, W. Trog, K. De Meyer,
B. De Ceulaer, M. Moonen, P. Vandaele, "High-speed modem for a
communication network," to IMEC vzw, Belgium and Siemens
Atea, Belgium.
US Patent 6,584,147
Europe Patent 0887974A1
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