We have research projects in four areas
- Trustworthy Hardware Design:
- Side-channel analysis of embedded hardware and software
- Hardware accelerators for cryptography
- Multi-core design of Cryptography
- Design Methods for Secure Hardware and Software.
- Physical Unclonable Functions:
- PUF design in ASIC and FPGA
- True Random Number Generators
- Large-scale Measurement of FPGA PUF
- Environmental Testing of FPGA Designs
- Novel Statistical Methods for PUF Analysis
- Cryptographic Benchmarking and SHA-3
- Performance Evaluation of SHA-3 Candidates in ASIC and FPGA
- Benchmarking of ASIC and FPGA Crypto Implementations
- Measurement and Analysis of FPGA Power Dissipation
- SHA-3 ASIC Prototype
- Sensor Node Design
- Cosimulation of Hardware, Software and Network
- Intellectual Property Protection in Sensornets
- Field Programmable Gate Array based Sensor Node
In this project, we investigate the design of high-performance, and embedded hardware implementation of cryptography. We are particularly interested in implementations that are resistant against side-channel analysis attacks and/or fault attacks.
This research is supported by the following grants.
- I. Kim, P. Schaumont, TC: Small: New Directions in Side Channel Attacks and Countermeasures, NSF Trustworthy Computing Award 1115839, 8/11 - 7/14.
- P. Schaumont, CAREER: Hardware/Software Codesign for Secure Embedded Systems: Methods and Education, NSF Trustworthy Computing Award 0644070, 1/07 - 12/11.
We have developed a hardware-software codesign environment, called GEZEL.
In this project, we are developing robust physical unclonable functions suitable for implementation in Field Programmable Gate Array or ASIC. We have also invested effort into characterizing a large collection of FPGA's, and we are providing this data online.
This reseach is supported by the following grants.
- P. Schaumont, II-NEW: Infrastructure to Collect and Analyze Circuit Variability in FPGAs, NSF Computing Research Infrastructure, 9/09 - 8/12.
- P. Schaumont, L. Nazhandali, I. Kim, TC: Medium: From Statistics to Circuits: Foundations for Future On-chip Fingerprints, NSF Trustworthy Computing Program, 8/10 - 7/13.
Our database with FPGA variability measurements is available online.
In this project, we are designing a methodology for benchmarking ASIC implementations of cryptographic hardware. We have designed an ASIC with the SHA-3 round-3 candidates. This ASIC is pin-compatible with the SASEBO-R board.
This reseach is supported by the following grants.
- K. Gaj, J. Kaps, L. Nazhanali, P. Schaumont, D. Bernstein, Environment for Fair and Comprehensive Performance Evaluation of Cryptographic Hardware and Software , NIST grant 60NANB10D004, 1/2010-12/2012.
Data on our SHA-3 chip, and related publications, are found on a dedicated webpage.
In this project, we are investigating the use of Low-power Field Programmmable Hardware as a programmable component on a Sensor Node. We are designing a simulator, called SUNSHINE, to develop sensor node applications for such a sensore node. We are also building a prototype for such a hybrid (hardware/software) sensor node.
This reseach is supported by the following grants.
- Y. Yang, P. Schaumont, NetSE: Cross-domain Design Tools for Sensor Network and Architecture, NSF Network Science and Engineering Program, 8/09 - 7/12.
The SUNSHINE project is open source, and can be downloaded from a separate web page.