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Winter 2004

CPEs Creating Efficiency Tools For Design, Testing, Verification

New contracts from Intel and the NSF will add to the slate of tools that Michael Hsiao's team is developing to reduce IC design, testing, and verification time.

70 Percent of Design Time
"Due to increasing complexity, about 70 percent of the design time for semiconductor chips is now dominated by verification and troubleshooting design errors," Hsiao said. This motivates him to develop tools to make testing and verification more efficient and to create design techniques that relieve the high cost of design verification and vector generation.

"We have already achieved an order-of-magnitude breakthrough toward our goal of reducing verification costs, and we hope to have another breakthrough soon," he said.

Verification Algorithms for Sequential Systems
Working with a $225,000 grant from the NSF, Hsiao's team is developing graph-theoretic algorithms to improve the design verification for large and complex sequential systems. They are working to develop novel automatic test pattern generation (ATPG) techniques to use where conventional binary-decision-diagram (BDD) approaches fail.

"We seek a new ATPG algorithm that intelligently prunes search spaces that are redundant due to overlapping solutions," he said. "This approach should accelerate the search for all solutions and significantly cut verification time."

Intelligent ATPG for Delay Testing
Improving the testing of high-performance chips is the goal of Hsiao's $120,000 contract with Intel. "Higher clock rates, shrinking geometries, longer wires, and increased density make chips more vulnerable to speed-related failures," he said.

"It's already a daunting task to test a 3 GHz chip. It is critical to ensure that each chip works at the correct processor speed and that it won't fail at the rated clock," he said. "But testing will become even more of a problem as Intel move to the next generation processor with speeds greater than 3 GHz."

Hsiao's team is studying the interaction between functional paths within the sequential search space and delay defects. "We are addressing the testing issues on delay-related defects, with a goal of shrinking the delay test pattern size and the potential yield loss."

The NSF and Intel efforts will add to the verification and design tools developed by Hsiao's team, including the recent software to identify hidden errors and defects in system-on-a-chip designs.

 

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Last updated: Tue, Apr 20, 2004