While scientists and engineers work to develop ultra-miniature devices that are measured in nanometers, other researchers are working to define and change design techniques to make sure that such small devices can actually be usable.
Molecular electronics, quantum computing, single-electron transistors, and even standard silicon technology reaching nano-scale, will all introduce greater uncertainty and unreliability into circuit and system design, according to Sandeep Shukla, who is working to develop reliability techniques and measures for defect-tolerant architectures for the nanotechnology era.
"Devices of the several-nanometer size will have a high degree of failures and uncertainties and we must be able to design systems that incorporate failure rates and uncertainties as design parameters," he said.
Manufacturing Defects, Transient Faults, & Aging
"Nano-devices will fail due to manufacturing defects, transient faults from reduced noise tolerance at low voltage and current levels, and faults due to aging because of molecular techniques used in creating the devices," he explained. "Although nano-scale manufacturing will allow us to pack more devices on a chip, we will have to live with these possibilities of defects in the nano-substrate."
Currently, design engineers can almost always safely assume that transistors and logic gates will behave as predicted by theory. "With uncertainties being rampant in nano-technology, we can only rely on the measures of the probability that a transistor will behave correctly, or a logic gate function correctly," he said. To implement a logic function with a high degree of reliability, engineers will have to build redundancy in the design.
"Because of the large number of devices per unit area, redundancy of devices will be acceptable," Shukla said, "however, preliminary experiments show that increased redundancy may lead to reduced reliability of the computation. This necessitates a need for tools in the hand of designers that allows them to model probabilistic nature of defects and automatically evaluate the reliability-redundancy trade-offs very quickly to decide between design alternatives."
With funding from an NSF Small Grant for Exploratory Research (SGER), Shukla is developing tools for such redundancy/reliability tradeoff with the goal of designing and evaluating defect-tolerant architectures for nanotechnology. His efforts are based on formal methods applied to probabilistic models and their verification.
Although he has significant experience with these techniques, he said the work is more challenging at the nano-scale. "Numerical accuracies in small probabilities at nano-scale present a challenge and the entropy of nano-systems is much higher," he said.
System Design Expertise
An expert in formal methods and verification, as well as system level design and embedded systems, Shukla is involved in several systems design and automation efforts. He has an NSF CAREER award to create design automation tools for and is a co-investigator on a project for the Semiconductor Research Corp. that is developing system models for provably correct component compositions in system-level designs.