2:00 PM - 2:30 PM on Friday, February 21, 2014
Location: Lavery Hall 320
by Sarvesh Prabhu, Ph.D. candidate, ECE Department, Virginia Tech
Logic Built-in self test (LBIST) is a popular technique for on-chip at-speed testing of digital circuits. In LBIST, output compression techniques are used to reduce hardware overhead of storing test responses but such compression makes diagnosis extremely challenging. I present a new property checking-based LBIST architecture which uses hardware monitors to check certain properties in the output responses. If any property is violated, the failing property number is stored for diagnosis. The proposed architecture improves diagnosability considerably with minimal hardware overhead. The experimental results show that the diagnostic resolution achieved by the new architecture is comparable to the diagnostic resolution achieved in a non-BIST setup for many circuits.
Sarvesh Prabhu is a PhD student in Virginia Tech since the fall of 2009. He is working on his dissertation "Techniques for enhancing test and diagnosis of digital circuits" under Dr. Michael S. Hsiao. Sarvesh received his BE in electronics and telecommunication from University of Pune in India in 2007. Before joining VT he worked in cognizant technology solutions for 2 years. He completed his MS in Computer Engineering at VT in Spring 2012 after which he interned in Intel Corporation for 7 months before resuming his PhD research.
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