Importance of the dielectric
Goley explains that “industry has transitioned from silicon dioxide as the main gate oxide to using Hafnium oxide (HfO2), which has a much larger dielectric constant. When you use HfO2 with germanium however, the materials like to interdiffuse, creating lots of defects that diminish channel mobility.”
Previously, if you wanted to increase the gate capacitance of a transistor you had to make the oxide layer thinner. The layers had become so thin, however, that electrons were jumping across it and generating leakage current, which wastes power. With HfO2, a thicker layer can provide the same high capacitance without the waste. “We need the higher oxide capacitance so that we can drive more current in the devices,” says Kundu. “My plan is to improve the oxide capacitance that ultimately increases the transistor performance.”
Minimizing the defects
Undergraduate Peter Nguyen has spent two semesters doing research in the Advanced Devices & Sustainable Energy Laboratory, and will continue there for graduate work, where he will implement Ge-based FinFETs as another alternative for low-power, cost-effective, and fast transistors. His undergraduate research has been to identify and to minimize the defects that occur when growing one substrate on top of another.
Nguyen has been working on an annealing method, which involves heating the devices to 400-700 degrees C. “What ends up happening is that the crystal lattice realigns itself in the process, which alleviates some of the defects,” he explains. His job was to find the optimal thermal budget, or the amount of thermal energy transferred to the device, in order to reduce defects.
Nguyen, who came to Virginia Tech knowing that he wanted to study semiconductors, is enjoying his experiences: “I like the characterization aspect and being able to fabricate the transistors. I haven’t had that experience yet, but it’s fascinating. You do learn a lot from lectures and classes, but research is the frontier.”
Mantu Hudait, an associate professor of ECE, and his research team at the Advanced Devices & Sustainable Energy Laboratory (ADSEL) are growing the next advances in transistor and solar technology. They are working at the atomic level to heterogeneously integrate different materials on low-cost silicon substrate.
From left: Souvik Kundu, Nikhil Jain, Mantu Hudait, Yan Zhu, Michael Clavel, and Patrick Goley.
Their goal is to take advantage of the low cost and manufacturability of silicon, while extending its speed, power, and efficiency. Ultimately, they want to make computing devices faster and reduce power needs as well as improve the efficiency and affordability of solar cells.
The researchers include Ph.D. students Nikhil Jain and Yan Zhu, master’s students Patrick Goley and Michael Clavel, undergraduate researcher Peter Nguyen. Souvik Kundu, a post-doctoral researcher, recently joined the group.
A project that interests most computer users is creating faster microprocessors. Hudait explains that today’s technology has nearly reached the full potential of silicon, and that other options must be explored. The most cost-effective options should still be able to make use of the extensive knowledge base in place for silicon. “If we want to continue to increase performance at the same rate, there’s no clear way to continue to do it with silicon,” he says. “We will need to switch to new channel materials.”
Two of the materials the group is working with are germanium (Ge) and indium gallium arsenide (InGaAs). These materials have higher carrier mobilities, which give them the potential for faster speeds. However, there are challenges and disadvantages that go along with this: higher cost and a problematic chemical reaction with the oxide layer.
First, the cost of Ge and GaAs is significantly higher than that of silicon. To take advantage of silicon’s research base and lower cost, the group is using thin layers of germanium layered on top of a “virtual” silicon base. The problem with this, explains Zhu, is that the crystalline structure has a different spacing between the atoms of the two materials. When germanium is grown on top of the silicon, it tries to adapt to silicon’s spacing, causing flaws in the chip.
Yan Zhu works inside the hood, where he prepares the substrates for chips.
Second, germanium doesn’t play as well as silicon with the necessary oxide layer. The oxide layer forms a dielectric that separates the gate from the channel in a transistor. According to Goley, “silicon dioxide gives you a nearly perfect interface between the oxide and the silicon channel. Doing that with germanium is much more complicated. Germanium likes to interdiffuse with oxide layers, which creates more charge imbalance, leading to more scattering,” Goley says, thus decreasing carrier mobility. “We’re going through all this trouble to change to germanium, and by the time you put the oxide layer on, the channel mobility has been degraded to the level of silicon,” asserts Goley.
The team is currently working on solutions to the Ge interface problem. “Starting with a very thin layer of thermally grown germanium oxide,” Clavel explains, “we preserve the quality of the interface and then protect it using a layer of diffusion-resistant aluminum oxide.”
Clavel is also exploring other oxides, such as tantalum pentoxide (Ta2O5) and tantalum silicate (TaSiOx), mentioning that tantalum-based oxides have been well-researched for memory applications. To deposit these oxides, the ADSEL researchers use atomic layer deposition (ALD), explains Clavel, whose labmates call him ‘marathon man’ because of his long hours in the cleanroom working with these materials. “ALD is literally growing oxides one layer at a time. We’re engineering the oxide at the atomic level, building it step by step.” According to Clavel, this method results in high quality oxides that help improve the electrical characteristics of their devices. “We’re still in the early phases of the project, but we’re excited about the progress we’ve made so far,” says Goley.
Lower power devices
Not only is the ADSEL group trying to make faster transistors, they’re also reducing their power consumption. “With each transistor getting smaller, the performance is increasing,” notes Zhu, “but the leakage power is also increasing sharply.” He is working to create a device that can be operated at low power without sacrificing speed.
Central Processing Units (CPUs) use Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) that require a certain amount of energy to force electrons to jump the energy barrier and operate the device. Zhu is working on Tunnel Field Effect Transistors (TFETs) that instead use controlled quantum tunneling to move through the barrier. “This device can be operated at a very lower power,” he explains.
"We’re using new materials, new growth techniques, and new architectures,” says Zhu. Using group III-V materials (such as InGaAs) and Ge, they can create transistors with a lower band gap energy and higher carrier mobility. “So we can operate with lower voltage at higher speeds.” They grow their materials using molecular beam epitaxy (MBE), which uses an ultra-high vacuum to eliminate contamination. “The pressure is very low inside the growth chamber,” Zhu notes, “the vacuum level is almost as high as on the moon.” They also use a new device architecture called vertical device architecture instead of the traditional planar architecture. “We have several different designs to upgrade the device performance….Our performance is promising,” he says.
Aside from faster and lower energy computers, Zhu stresses that these improvements could impact many areas of our lives. It can be used inside microprocessors and memory for next generation computers, but because battery life will be better, it can also be implanted inside humans for biomedical applications. “Using MOSFETs costs a lot of power and generates a lot of heat,” he says, “also, if we can use TFETs people won’t have to change the batteries as often.”
More efficient solar cells
Testing of their first batch of solar cells has already demonstrated high efficiency.
By integrating III-V materials onto a silicon substrate, the team is also helping to create affordable, highly-efficient solar cells combining the high-efficiency of GaAs with the low cost of silicon. According to Jain, most solar cells use silicon materials, and their efficiency is only about 25 percent at best. Most commercial solar cells are limited to 21-22 percent by production constraints.
Triple junction solar cells, Jain admits, already use GaAs and can manage up to 44 percent efficiency. “These kinds of solar cells have dominated the space market,” he says. “In space, you really care about performance. For terrestrial applications, cost is the driving force.”
GaAs solar cells are expensive. Producing a GaAs solar cell that is approximately half the size of a silicon cell, may cost more than twice as much, according to Jain.
“It’s all a numbers game,” says Jain. “We need new approaches to target high performance at a lower cost. The winning technology for the future would be the one that combines the best of both.”
To make these solar cells both efficient and affordable, Jain is working to integrate GaAs onto silicon. “Researchers tried this back in the 1980s, but the performance wasn’t good. We’re trying something different,” he says. “The way we're growing these materials for solar cells and fabricating them is novel for this kind of work.” He stresses that even if they can manage 25 percent efficiency for these cells that will be remarkable. “This is a disruptive solar technology that I believe can be transformative.”