Secure Embedded Systems at Virginia Tech researches the design and implementation of secure hardware design.
Standardizing crypto evaluations, benchmarks
When evaluating cryptographic algorithms, security is paramount, but speed is also important. A fast, secure algorithm is better than a slow, and equally secure one.
The problem in evaluating the performance of cryptographic hardware and software is a lack of consistent benchmarks, according to Patrick Schaumont, director of the Secure Embedded Systems Laboratory.
Schaumont and Leyla Nazhandali have received a three-year, $544,257 grant from the National Institute of Standards and Technology (NIST) to provide a consistent system for evaluating cryptographic algorithms in both hardware and software. They are members of a multi-university team that includes George Mason University and the University of Illinois at Chicago.
“Typically cryptographic algorithms have been standardized after an open competition overseen by a government agency,” explained Schaumont. The benchmarks focus on software performance on personal computers and are not sufficient to predict speed and power usage on DSPs or FPGAs, or even custom-design ASICs, he added.
The Virginia Tech team will lead the benchmarking methods for performance of cryptography when implemented as an ASIC. Schaumont will also advise the team at the University of Illinois that will work on cryptographic software performance on small microprocessors and computers.
The resulting evaluation process will allow users to profile their hardware designs in a comprehensive process that covers FPGA as well as ASIC. An important driver application for this project on the short term is the ongoing competition organized by NIST to define SHA-3, the next-generation hash standard.