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2004 Annual Report


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Beyond Imaging

Photonic Biomedicine

Cell Behavior

No-Kill Sensors

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Hokie Suit

Software Design

 
ECE Research Update

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Cognitive Radio

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IPEMs

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R&D 100 Award

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$1000 Elevator

Embedded Systems

Defect Tolerance

Efficiency Tools

Pervasive Networks

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2002/2003 Ph.D.s

2003 Patents

 

 

 

Special Report:
ECEs and Biomedicine

April 2004

 

For more information, visit the PROACTIVE website.

Efficiency tools for IC design, testing, verification

The PROACTIVE laboratory is developing software tools to reduce IC design, testing, and verification time, which now comprise 70 percent of design time.

Under a new grant from the NSF, the team, headed by Michael Hsiao, is developing revolutionary graph-theoretic algorithms to improve the design verification for large and complex sequential systems. They are developing novel automatic test pattern generation techniques to use where conventional binary-decision-diagram (BDD) approaches fail. Recent results show that an order of magnitude improvement in computational complexity can be achieved with the proposed approach.

Improving the testing of high-performance chips is the goal of a new contract with Intel. Higher clock rates, shrinking geometries, longer wires, and increased density make chips more vulnerable to speed-related failures. “Our research is to address global sequential testing issues on delay-related defects, with a benefit of both reducing delay test pattern size and potential yield loss.”

 
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Last updated: Wed, Jun 9, 2004