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April 2003
For further information, please see the following:

Michael Hsiao

Software Program Identifies Hidden Errors, Defects For Testing, Verification of System-on-a-Chip Design

A Virginia Tech software program that uses logic conflicts to identify untestable faults may improve design verification of large system-on-a-chip (SoC) VLSI circuits.

Continuing advances in the semiconductor technology have made possible the development of very large system-on-a-chip (SOC) VLSI circuits. “Nevertheless, it is impossible to build such systems without errors or defects introduced during the design process,” said Michael Hsiao, who developed the program. “In order to reduce both space and computational complexity during testing, it is critical that useful global information and constraints be identified and extracted efficiently, without being burdened by the design size,” he said.

Current automatic test pattern generators (ATPGs) for large digital designs spend significant computational effort on identifying untestable faults in both combinational and sequential circuits. “These faults are those that no vector sequence is able to detect; they are either unexcitable, unpropagatable, or both, due to reconvergent fanouts in the circuit. For such faults, the excitation/ propagation criterion requires conflicting value assignments in the circuit. For sequential circuits, conflicting values may also include unreachable state assignments. Given enough time and backtrack limits, deterministic ATPGs can identify all untestable faults via exhaustive search. However, this may be prohibitively expensive,” he said.

Hsiao’s software, based on a newly developed theory, quickly and efficiently identifies a large number of logic implications in a sequential circuit. Next, by maximizing conflicts locally around each logic gate, it tries to identify faults that are untestable due to these logic conflicts. Impossible value combinations around each gate in the circuit are discovered, where previous methods failed to identify. This technique has identified the maximum number of untestable faults for many circuits in reported literature. The complexity of this new algorithm is extremely low, and it is maintained to be linear with respect to the circuit size, making it very attractive. “This technology can potentially enable the area of the design verification as the powerful implications derived can identify relationships among regions within the circuit,” he said.

 
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Last updated: Thu, Jun 26, 2003