Michael S. Hsiao is currently a Professor in
The Bradley Department of Electrical and
Computer Engineering at Virginia Tech.
He received his B.S.
in Computer Engineering, M.S. and Ph.D. in Electrical Engineering, all
from the University of Illinois at
Urbana-Champaign. He had held positions at
Digital Equipment Corporation,
National Semiconductor Corporation,
NEC USA, Intel Corp., and
Rutgers University.
He is a recepient of the National Science Foundation Faculty Early Career
Development (CAREER) Award.
His current research interests include
architectural-level and gate-level automatic test pattern generation (ATPG),
design verification and diagnosis,
fault simulation and defect coverage evaluation,
design for testability (DFT),
test set compaction,
power estimation and management in VLSI,
computer architecture,
parallelization, and
reliability.
Research
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PROACTIVE Testing, Verification, and Power Management Research Group
-
Publications
-
Research Members
and
A few pictures of us
- Benchmarks and Conferences
- Recent Research Highlights
- How to utilize swarm intelligence in test and verification (see our publications in DATE2008, ICCD2008)
- On detecting and isolating hardware malicious insertions (see our publications in HOST2008, GLSVLSI2008)
- How to apply deductive and inductive learning methods for bounded model checking and induction
(see our publications in VLSI2007, DAC2006, HLDVT2005, CHARME2005, DAC2005, ICCAD2004, IWLS2004)
- How to mine global constraints for sequential circuit equivalence checking
(see our publications in DAC2006, HLDVT2005)
- New fast methods for fault collapsing to unprecedented small fault sets
(see our publications in VTS2006)
- How can we apply ATPG to formal verification without exponential time? New type of learning is needed!
(see our publications in ITC2004, DATE2004, DATE2003, HLDVT2003)
- Intelligent simulation for design validation via partitioning and abstraction (see our publications in ITC2006, TC2006, TCAD2006, HLDVT2005, ITC2004, VTS2004, ITC2003)
- New QBF solver using resolution and ZBDDs
(see our publications in VLSID2005)
- Fast untestable stuck-at, bridging, and transition fault identification
(see our publications in ITC2006, TCAD2006, ATS2005, ICCD2005, VTS2004, ITC2004, VLSI2004, DATE2003, DATE2002)
- Non-conventional global learning for equivalence and model checking (see our publications
in ICCD2005, VLSI2004, HLDVT2003)
- New path-delay and transition fault model and testing (see our publications
in TODAES2005, DATE2005, ITC2004, ITC2003, TODAES2004, ITC2002)
- How to reduce yield-loss by avoiding functionally impossible transitions (see our publications in DT2005, DFT2003)
- Architectural and high level test generation (see our publications in
ATS2003, ITC2003, TCAD2006)
- Test data volume and test application time reduction for transition tests
(see our publications in ITC2002, ETW2002, JETTA 2003)
- Spectral methods for sequential circuit testing (see our publications
in TC2006, ICCAD2002, VTS2002, DATE2002, VTS2001, DATE2001)
- Fast fault and error diagnosis using region-based model (see our publications
in ITC2001, VLSI2001)
- Architectural level power management (see our publications in ICCD2005, ISLPED2005, DATE2005, PACS2002, ISLPED2001, PACS2001)
Honors
- Most influential papers of 10 years (1998-2007) of Design Automation and Test in Europe (DATE) Conference
- Virginia Tech Dean's Faculty Fellow
- National Science Foundation Faculty Early Career Development (CAREER) Award
- Digital Equipment Corporation Fellowship
- McDonnell Douglas Scholarship
- Highest Graduating Honors
- NSF Undergraduate Research Fellowship
Teaching
- Fall 2008
- Spring 2007
- Other Courses Taught in the Past
Information for Students
Information for those interested in Graduate Research Assistantship.
Organizations and Groups
Personal Interests
Reading, tennis, table tennis, badminton, ice-skating, guitar-playing,
fine music, piano, being with family and friends.
Visitors since 1997 |
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Last Modified: January 2007
