JoAnn M Paul

Selected publications in Chip Heterogeneous Multiprocessing

Capacity Metric for Chip Heterogeneous Multiprocessors
Mwaffaq Otoom and JoAnn M. Paul
9th International conference on Hardware/software codesign and system synthesis (CODES+ISSS 11), Oct. 2011 -- to appear

Workload Mode Identification for Chip Heterogeneous Multiprocessors
Mwaffaq Otoom and JoAnn M. Paul
International Journal of Parallel Programming -- to appear in 2011

Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors
Alex Bobrek, JoAnn M. Paul, and Donald E. Thomas

IEEE Transactions on Computers 59(10): 1402-1418 (2010)

The Emerging Landscape of Computer Performance Evaluation
JoAnn M. Paul, Mwaffaq Otoom, Marc Somers, Sean M. Pieper, and Michael J. Schulte

Advances in Computers 75: 235-280 (2009)

Holistic Design and Caching in Mobile Computing
Mwaffaq Otoom and JoAnn M. Paul

6th International conference on Hardware/software codesign and system synthesis (CODES+ISSS 08), Oct. 2008, pp. 115-120.

Webpage-Based Benchmarks for Mobile Device Design
Marc Somers and JoAnn M. Paul
Asia and South Pacific Design Automation Conference (ASPDAC) 2008, Jan. 2008, pp. 795-800.

Interrupt Modeling for Efficient High-Level Scheduler Design Space Exploration
F. Ryan Johnson and JoAnn M. Paul
ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 1, Jan. 2008, pp. 1-22.

Event-based Re-training of Statistical Contention Models for Heterogeneous Multiprocessors
Alex Bobrek, JoAnn M. Paul and Donald E. Thomas
5th International conference on Hardware/software codesign and system synthesis (CODES+ISSS 07), Sep. 2007, pp. 69-74.

A New Era of Performance Evaluation
Sean M. Pieper, JoAnn M. Paul and Michael J. Schulte
Computer, Vol. 40, No. 9, Sep. 2007, pp. 23-30.

Shared Resource Access Attributes for High-Level Contention Models
Alex Bobrek, JoAnn M. Paul and Donald E. Thomas
Proceedings of the 44'th Design Automation Conference, Jun. 2007, pp. 720-725.

Amdahl's Law Revisited for Single Chip Systems
JoAnn M. Paul and Brett H. Meyer
International Journal of Parallel Programming, Vol. 35, No. 2, Apr. 2007, pp. 101-123.

Scenario-Oriented Design for Single-Chip Heterogeneous Multiprocessors
JoAnn M. Paul, Donald E. Thomas and Alex Bobrek
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 8, Aug. 2006, pp. 868-880.

What's in a Name?
JoAnn M. Paul
Computer, Vol. 39, No. 3, Mar. 2006, pp. 87-89.

Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffery E. Nelson, Sean M. Pieper and Anthony G. Rowe
IEEE Transactions on Computers, Vol. 54, No. 6, Jun. 2005, pp. 684-697.

High-Level Modeling and Simulation of Single-Chip Programmable Heterogeneous Multiprocessors
JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy
ACM Transactions on Design Automation of Electronic Systems, vol. 10, no. 3, Jul. 2005, pp. 431-461.

Scenario-Oriented Design for Single Chip Heterogeneous Multiprocessors 
JoAnn M. Paul
Proceedings of the 19th IEEE international Parallel and Distributed Processing Symposium, Apr. 4-8 2005.

Benchmark-Based Design Strategies for Single Chip Heterogeneous Multiprocessors
JoAnn M. Paul, Donald E. Thomas, and Alex Bobrek
Proceedings of the 2nd International Conference on Hardware/Software Codesign and System Synthesis,
Sep. 2004, pp. 54-59.

High Level Cache Simulation for Heterogeneous Multiprocessors
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, and Faraydon Karim
Proceedings of the 41st Design Automation Conference, June 7-11 2004 pp. 287-292.

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, and Donald E. Thomas
Proceedings of Design, Automation and Test in Europe, Feb. 16-20 2004.

Programmers' Views of SoCs
JoAnn M. Paul
Proceedings of the 1st International Conference on Hardware/Software Codesign and System Synthesis,
Oct. 1-3 2003, pp. 156-181.

Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors
JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson Joshua J. Pieper, and Donald E. Thomas
Proceedings of the 40th Design Automation Conference, June 2-6 2003, pp. 408-411.

Layered, Multi-Threaded, High-Level Performance Design 
Andrew S. Cassidy, JoAnn M. Paul, and Donald E. Thomas
Proceedings of Design, Automation and Test in Europe, Mar. 3-7 2003, pp. 954-959.

System-Level Modeling of a Network Switch SoC 
JoAnn M. Paul, Christopher P. Andrews, Andrew S. Cassidy, and Donald E. Thomas
Proceedings of the 15th International Symposium on System Synthesis, Oct. 2-4 2002, pp. 62-67.

The Design Context of Concurrent Computation Systems
JoAnn M. Paul, Christopher M. Eatedali, and Donald E. Thomas
Proceedings of the 10th International Symposium on Hardware/Software Codesign, May 6-8 2002, pp. 19-24.

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems 
JoAnn M. Paul and Donald E. Thomas
Proceedings of Design, Automation and Test in Europe, March 4-8 2002, pp. 522-528.

Modeling and Simulation of Steady State and Transient Behaviors for Emergent SoCs 
JoAnn M. Paul, Arne J. Suppé, and Donald E. Thomas
Proceedings of the 14th International Symposium on Systems Synthesis, Sep. 30-Oct. 3 2001. pp. 262-267.

Modeling and Evaluation of Hardware/Software Designs
Neal K. Tibrewala, JoAnn M. Paul, and Donald E. Thomas
Proceedings of the 9th International Symposium on Hardware/Software Codesign, Apr. 2001, pp. 11-16.

A Codesign Virtual Machine for Hierarchical, Balanced Hardware/Software System Modeling 
JoAnn M. Paul, Simon N. Peffers, and Donald E. Thomas
Proceedings of the 37th Design Automation Conference, June 5-9 2000, pp. 390-395.

Frequency Interleaving as a Codesign Scheduling Paradigm
JoAnn M. Paul, Simon N. Peffers, and Donald E. Thomas
Proceedings of the 8th International Workshop on Hardware/Software Codesign, May 2000, pp. 131-135

jmpaul@vt.edu
 
Last updated July, 2011