Fall 2013 textbook list
The Fall 2013 ECE textbook list is available online for students.
Current Prerequisites & Course Offering
For current prerequisites for a particular course, and to view course offerings for a particular semester, see the Virginia Tech Course Timetables.
ECE 5506 Testing and Verification of Digital Systems (3C)
Various topics on digital circuit testing and verification. 5506: circuit verification including two-level and multi-level circuit verification, sequential circuit verification, model-checking simulation-based verification, and ATPG-based verification.
5505 will provide the fundamental and state-of-the-art methods and knowledge on testing of digital systems, and 5506 will provide the fundamental and state-of-the-art techniques and knowledge for verification of electronic systems. As the number of gates on a chip increases drastically, testing of the manufactured chip becomes an important issue in circuit and system design. In order to test circuits/systems effectively, computer engineers need to understand various techniques of circuit testing. 5505 meets the need by teaching both basic and advanced concepts and underlying theories of circuit testing from the system level down through the gate level. Design verification has recently become a bottle-neck in the design process. Failure to detect errors early in the design stage can be prohibitively expensive to change late in the cycle. 5506, the verification portion of the course, emphasizes techniques and approaches to efficiently check if the circuit implementation is correct.
Typically offered: Spring. Program Area: Computers.
Prerequisites: Graduate Standing in ECE.
Graduate standing in ECE is assumed in order to have the undergraduate foundation in computer design.
Department Syllabus Information:Major Measurable Learning Objectives:
- verify two-level using tautology checks,
- construct binary decision diagrams,
- use BDDs to verify complex multi-level circuits,
- verify sequential circuits,
- specify formal properties and specifications,
- check models using computational tree logic,
- compute simulation-based verification.
|Intro and Graph Algorithms||10%|
|Two-Level Circuit Verification & Tautology||15%|
|Binary Decision Diagrams||15%|
|Multi-Level Circuit Verification||15%|
|Computational Tree Logic||15%|
|Symbolic Model Checking||10%|