Recent News:
Multi-thread multi-core...a single bug (2012 Annual Report)
Virginia Tech researcher eyes automated process in debugging complex concurrent software (January 2012)
Office: 353 Durham Hall
Mailing Address: 302 Whittemore (0111)
Virginia Tech
Blacksburg, VA 24061
Tel: (540) 231-6904
Fax: (540) 231-3362
vt.edu Email: chaowang
Affiliated Research Group
Center for Embedded Systems for Critical Applications (CESCA)
Title: Assistant Professor
Education:
Ph.D. University of Colorado at Boulder, 2004
M.S. E.E., Peking University, China, 1999
B.S. E.E., Peking University, China, 1996
Teaching Interests:
Testing and verification, algorithms and data structures, concurrent programming
Research Interests:
Automated verification, software engineering, programming languages
- V. Kahlon and C. Wang, “Lock removal in concurrent trace programs,” CAV, 2012.
- C. Wang, M. Said, and A. Gupta, “Coverage guided systematic concurrence testing,” ICSE, 2011.
- N. Sinha and C. Wang, “Interference abstraction,” POPL, 2011.
- N. Sinha and C. Wang, “Staged concurrent program analysis,” FSE, 2010.
- V. Kahlon and C. Wang, “Universal Causality Graphs: A Precise Happens-Before Model for Detecting Bugs in Concurrent Programs,” CAV, 2010.


