EE/CPE Teams Denoise EKG Signals
CPE hardware design students EE systems students have been teaming up to design and implement digital filters to denoise electrocardiogram (ECG or EKG) signals.
For their Capstone Design Project, students from ECE 4514, Digital System Design II, and ECE 4624, DSP and Filter Design, form intradisciplinary teams that model those of the workplace. One DSP systems engineer and two FPGA hardware design engineers comprise each team, and each member contributes different knowledge and expertise.
"The design of digital filters can offer fascinating experiences for capstone projects," said Jim Armstrong, who teaches Digital System Design II. "The design of digital filters, however, requires knowledge of both theoretical filter design as taught in a mathematically based DSP course and implementation of the filter on a logic card as taught in a course teaching hardware description languages and synthesis." Armstrong was part of the faculty team that initially conceived the project, along with Amy Bell, Gail Gray, and Louis Beex.
Instead of requiring a two-course sequence, the faculty team decided to create a capstone project involving both courses. Students gain appropriate background in each course, then collaborate in the final third of the semester on the capstone project.
The project goal is to design, implement, and test a digital bandpass filter to denoise a sampled ECG signal while retaining important signal (Continued from page 1.) characteristics. The filter's passband edges must correspond to 7Hz and 35Hz for a sampling frequency of 250Hz.
The DSP students are required to design a range of FIR and IIR filters and select a solution that meets the constraints imposed by the hardware. "The DSP student design the filters using MatLab and theoretical process, then give the diagram to the digital design students," Armstrong said.
The hardware designers then must meet the requirements specified by the system level filter design - using the smallest FPGA space possible. "The digital design students then synthesize a VHDL model, translate is to code and to the FPGA," he said. "Both years that we have done this, our project success rates have been high," he said. "The students enjoy the open-ended problem and team experience," he added.