EE Goes Soft
As circuits and computers get more complex, design and hardware engineers turn even more to information technology to do their work. Through the use of languages, such as VHDL, engineers can build soft prototypes to check their logic instead of using hardware prototypes. This saves time and money. Virginia Tech was the first university to teach undergraduate and graduate students VHDL.
Either VHDL code, or high-level graphics-based design tools (bottom ) can be used to generate gate diagrams (top).
"EE is in the middle of a revolution," he said. "Fewer people are designing detailed hardware, and more are moving to software. Within the next five to 10 years, engineers will sit at a computer, write a program to design their hardware and check it out, then use a software tool to synthesize the design," he explained. "We're moving to full automation."
VHDL, a digital hardware description language, has been particularly powerful in this revolution. VHDL is a computer language that enables engineers to develop soft prototypes.
"With VHDL we can describe the computer we want to build, then simulate it by putting in our inputs and outputs and seeing if it does the right thing. Then we feed the description into a synthesis tool that automatically develops the circuit and gives us a gate diagram. At present, we can't design an entire large computer that way, but we do it in chunks, then connect the chunks manually," Armstrong said.
"VHDL is a way to describe a computer system without getting lost in the details. We used to draw these gates on paper or on the computer, but with up to 20,000 gates, it is easy to lose perspective. Now we create high-level models and analyze them."
Reconstructing Old Components
The language is not used only for designing new hardware, but sometimes for reconstructing old components. For example, the U.S. Department of Defense has used some parts for more than 40 years. "Originally these parts may have been made with vacuum tubes, then integrated circuits," Armstrong said. "Instead of trying to recreate the obsolete technology, which can be very difficult and expensive, we can describe the part in VHDL. This then becomes the documentation and part description, from which a synthesizer tool can design a state-of-the-art replacement."
VHDL models used for design can also be used to generate testing programs. Testing complex systems is as complicated as designing them. VISC researchers have been involved with developing VHDL-based tests for the DARPA Rapid Prototyping of Application-Specific Signal Processors (RASSP) program. The RASSP program involves developing equipment from off-the-shelf technology that can be updated through periodic upgrades. "In this case, we're using VHDL to recreate existing equipment," Armstrong commented.
VHDL was developed 10 years ago from a government program desiring six different contractors to be able to communicate their specifications. "After that, the IEEE took over the language and developed the standards that we use today."
Armstrong was on the IEEE standards committee, and along with Professor Gail Gray, has been instrumental in Virginia Tech becoming the first university to teach the language.
"This is a case of research being directly carried into the classroom," he said. "We were the first to teach it at either the graduate or undergraduate levels. We have educated more students in VHDL than any other place in the world.
"Our students don't learn the whole language, but use it as a CAD tool. They make models of little designs, simulate them, and check them out," he explained. "We also have them translate VHDL manually into a circuit so they can see how it works and so they can understand the automatic tools. Our undergraduates also take VHDL and synthesize field programmable gate array (FPGA) circuits."
Does the "softening" of electrical and computer engineering change what students should learn? "We need to teach the fundamentals, so that they can understand these systems. But maybe, when we teach fundamental circuits, we can also teach the design tools.
"The new engineers will write programs to design their hardware. We need to teach more software to our hardware engineers."
Modeler's Assistant - The Modeler's Assistant (MODAS) is an interactive graphics system that enables rapid development and test and VHDL models. MODAS relieves the the modeler of much of the burden of developing behavioral models and enforces a structured approach to modeling.
RASSP - VISC researchers are working with the Research Triangle Institute to develop two tools, the VHDL Test Bench Generator and the Signal Processing Algorithm Library, as part of the RASSP project.