Assistant Professor
Computer Engineering Group
Dept of Electrical and Computer Engineering
Virginia Tech

Mail Address:
302 Whittemore (0111)
Virginia Tech
Blacksburg, VA 24061

Email:
chaoh@vt.edu

Office:
357 Durham
Virginia Tech
Blacksburg, VA 24061

Tel: 540-231-5961
Fax: 540-231-3362

Education:

• Doctor of Philosophy, Eletrical Engineering, 2005
  Princeton University, Princeton, NJ, USA

• Master of Arts, Electrical Engineering, 2002
  Princeton University, Princeton, NJ, USA
  

• Bachelor of Engineering, Electrical Engineering, 1998,
  Tsinghua University, Beijing, P.R.China

Research Interests:

• Computer-aided design of application-specific integrated circuits

• Very large scale integration (VLSI) digital circuit design using standard cell libraries

• Distributed logic-memory architectures for memory-intensive applications

• Behavioral transformations targeting distributed implementations

• Computation-unit integrated memories and customized instruction generation

• Design with emerging nano-scale technologies

Teaching:

• ECE2574, Data Structure and Algorithms, Fall 2008

• ECE4514, Digital Design II, Summer 2008

• ECE5534, Electronic Design Automation, Spring 2008

• ECE2574, Data Structure and Algorithms, Fall 2007

• ECE5534, Electronic Design Automation, Spring 2006

• ECE2504, Introduction to Computer Engineering, Spring 2006 (Recitation)

• ECE2574, Data Structure and Algorithms, Fall 2005

• ECE3054, Electrical Theory, Fall 2005 (Recitation)

Publications:

Journal paper

• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Generation of heterogeneous architectures for memory-intensive applications through high-level synthesis," IEEE Trans. Very Large Scale Integration Systems (TVLSI), vol. 15, no. 11, pp. 1191-1204, Nov. 2007 [.pdf file].
  
  
• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Use of computation-unit integrated memories in high-level synthesis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 10, pp. 1969-1989, Oct. 2006 [.pdf file].
  
  
• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Generation of distributed logic-memory architectures through high-level synthesis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 11, pp. 1694-1711, Nov. 2005 [.pdf file].
  
  
• C.Huang, M. Wang, and Z. Wang, "An energy-efficient power supply controller for beam pumps," Oil Field Equipment (OFE, Chinese journal), vol. 28, no. 4, Nov. 1999.
  
  

Conference paper

• Y. Zheng and C. Huang, "Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability," accepted for publication in Proc. Conf. Design, Automation and Test in Europe (DATE), Apr. 2009 [.pdf file ].
  
  

• Y. Zheng and C. Huang, "A novel Toffoli network synthesis algorithm for reversible logic," accepted for publication in Proc. Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2009 [.pdf file ].
  
  

• Y. Zheng, M. Hsiao, and C. Huang, "SAT-based equivalence checking of threshold logic designs for nanotechnologies," in Proc. Great Lakes Symp. VLSI (GLSVLSI), May 2008, pp. 225-230 [.pdf file ].
  
  

• Y. Zheng and C. Huang, "Reconfigurable RTD-based circuit elements of complete logic functionality," in Proc. Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2008, pp. 71-76 [.pdf file ].
  
  

• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sept. 2005, pp. 239-242 [.pdf file ].
  
  

• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "High-level synthesis using computation-unit integrated memories," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2004, pp. 783-790 [.ps file] [.pdf file].
  
  
• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of heterogeneous distributed architectures for memory-intensive applications," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2003, pp. 46-53 [.ps file] [.pdf file].
  
  
• C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "High-level synthesis of distributed logic-memory architectures," in Proc. Int. Conf. Computer-Aided Design (ICCAD), Nov. 2002, pp. 564-571 [.ps file] [.pdf file].

Book

• L. Zhu and C. Huang, Master Microsoft Excel 2000 with Graphic Illustrations, China Machine Press, Beijing, 2000.