Leyla Nazhand-Ali Assistant Professor The Bradley Department of Electrical and Computer Engineering Virginia Tech

Mail Address: 302 Whittemore (0111) Virginia Tech Blacksburg, VA 24061 vt.edu Email: leyla Office: 331 Durham Tel: 540-231-4755 Fax: 540-231-3362

Education:

• Ph.D., Computer Engineering, 2006
  University of Michigan, Ann Arbor, MI USA
• M.S., Computer Engineering, 2002
  University of Michigan, Ann Arbor, MI USA
• B.S., Electrical Engineering, 2000,
  Sharif University of Technology, Tehran, Iran

Awards:

• NSF CAREER award titled, ″Overcoming Power Challenges in Embedded System Design With Subthreshold-Voltage Technology,″ 2008 NSF (0747262, CCF)
• IEEE Real World Engineering Projects Contest, 2008
• University of Michigan Computer Science and Engineering Honors Competition, first place, 2005
• Riethmiller Fellowship Award, University of Michigan, 2005-2006
• Dean’s list, Electrical Engineering Department, Sharif University of Technology, 1996-2000
  
  

Research Interests:

• Energy-constrained architectures, Subthreshold-voltage microprocessors
• Power analysis attack resistant embedded secure design using subthreshold-voltage techniques
• Code compression techniques for low-power embedded system design
• Engineering education focusing on the use of real-world engineering problems in freshman education

Teaching:

• Interests: Computer organization/architecture, Computer programming, Data structure and algorithms, Hardware description languages and logic design
• Fall 2006, Fall 2007: ECE 2500, Introduction to Computer Architecture
• Spring 2007: Nano-scale Energy Efficient Microarchitecture Design

Recent Publications:

• Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd Austin, Dennis Sylvester, David Blaauw, “Energy Efficient Subthreshold Processor Design,” to appear in Transactions on VLSI 09

• Michael B Henry, Leyla Nazhandali, "Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture, " to appear in HIPEAC 09

• Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, David Blaauw, “Exploring variability and performance in a sub-200-mV processor,” IEEE Journal of Solid-State Circuits, v 43, n 4, January, 2008, p 881-890

• Michael B Henry, Syed Imtiaz M Haider, Leyla Nazhandali, "A Low-Power Parallel Design of Discrete Wavelet Transform using Subthreshold Voltage Technology," International Conference on Compilers, Architecture and Synthesis for Embedded Systems CASES 08, Atlanta, Georgia, USA, 19-24 Oct. 2008

• Syed Imtiaz M Haider, Leyla Nazhandali, ″Utilizing Sub-threshold Technology for the Creation of Secure Circuits,″ IEEE International Symposium on Circuits and Systems ISCAS’0, Seattle, Washington, USA, 18-21 May 2008.

• Syed Imtiaz M Haider, Leyla Nazhandali, ″A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection,″ International Conference on Compilers, Architecture and Synthesis for Embedded Systems CASES’07, Salzburg, Austria, Sep. 30-Oct. 5, 2007.

• S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. Blaauw, ″Performance and variability optimization strategies in a sub-200mV, 3.5pJ/inst, 11nW subthreshold processor,″ IEEE Symposium on VLSI Circuits, 2007.

• B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, ″A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,″ IEEE Symposia on VLSI Technology and Circuits, 20, Honolulu, Hawaii USA, June 15-17, 2006.
• L. Nazhandali, M. Minuth, B. Zhai, and T. Austin, ″SenseBench: Toward an Accurate Evaluation of Sensor Network Processors,″ 2005 IEEE International Symposium on Workload Characterization IISWC’05, Austin, Texas USA, October 6-8, 2005.
• L. Nazhandali, M. Minuth, B. Zhai, J. Olson, T. Austin, and D. Blaauw, ″A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution,″ 2005 International Conference on Compilers, Architectures and Synthesis of Embedded Systems CASES’05, San Francisco, CA USA, September 24-27, 2005.

• L. Nazhandali, B. Zhai, R. Helfand, M. Minuth, J. Olson, S. Pant, A. Reeves, T. Austin, and D. Blaauw, ″Energy Optimization of Subthreshold-Voltage Sensor Processors,″ The 32^nd Annual International Symposium on Computer Architecture ISCA’05, Madison, Wisconsin USA, June 4-8, 2005.