leyla

Leyla Nazhand-Ali

Associate Professor
The Bradley Department of Electrical and Computer Engineering
Virginia Tech

 

Mail Address:
302 Whittemore (0111)
Virginia Tech
Blacksburg, VA 24061

vt.edu Email:
leyla

Office:
331 Durham


Lab:
371 Durham

Tel: 540-231-4755
Fax: 540-231-3362

 

 

 

 

Education:

 

 

 

 

Awards:

  • NSF CAREER award titled, ″Overcoming Power Challenges in Embedded System Design With Subthreshold-Voltage Technology,″ 2008 NSF (0747262, CCF)
  • IEEE Real World Engineering Projects Contest, 2008
  • University of Michigan Computer Science and Engineering Honors Competition, first place, 2005
  • Riethmiller Fellowship Award, University of Michigan, 2005-2006
  • Dean's list, Electrical Engineering Department, Sharif University of Technology, 1996-2000

 

 

 

 

Research Interests:

  • Energy-constrained architectures, Subthreshold-voltage microprocessors
  • Power analysis attack resistant embedded secure design using subthreshold-voltage techniques
  • Design of trustworthy chip identifiers
  • Code compression techniques for low-power embedded system design
  • Engineering education focusing on the use of real-world engineering problems in freshman education

 

 

 

 

 

Teaching:

  • Interests: Computer organization/architecture, Computer programming, Data structure and algorithms, Hardware description languages and logic design
  • Spring 2011: ENGE 1104, Exploring the Digital Future (freshman course)
  • Fall 2010: ECE 5504, Advanced Computer Architecture
  • Fall 2009: ECE 2534, Microprocessor System Design
  • Fall 2006, Fall 2007, Spring 2009: ECE 2500, Introduction to Computer Architecture
  • Spring 2007: Nano-scale Energy Efficient Microarchitecture Design

 

 

 

 

 

Current Graduate Students:

  • Dinesh Ganta, Ph.D.
  • Meeta Srivastav, Ph.D.
  • Lalleh Rafeei, M.S.
  • Yongbo Zuo, M.S.

 

Past Graduate Students:

  • Michael Henry, Ph.D. (2011)
  • Vignesh Vivekraja, M.S. (2010)
  • Kanu Priya, M.S. (2011)
  • Sinan Huang, M.S. (2011)

 

 

 

 

 

 

Publications:

  • Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont, ″ASIC Implementations of Five SHA-3 Finalists″, accepted to be published in DATE 2012.

 

  • M.B. Henry, L. Nazhandali, ″Design Techniques for Functional-Unit Power Gating in the Ultra-Low-Voltage Region″, 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012), Sydney, Australia, January 2012.

 

  • M.B. Henry, M. Srivastav, L. Nazhandali, ″A Case for NEMS-Based Functional-Unit Power Gating of Low-Power Embedded Microprocessors″, Design Automation Conference, San Diego, CA, June 2011, pgs 872-877.

 

  • X. Guo, M. Srivastav, S. Huang, D. Ganta, M. Henry, L. Nazhandali, P. Schaumont, "VLSI Characterization of SHA-3 Finalists,"14th Euromicro Conference on Digital System Design (DSD 2011), Oulu, Finland, August 2011 pgs 535 - 542.

 

  • X. Guo, M. Srivastav, S. Huang, D. Ganta, M. Henry, L. Nazhandali, P. Schaumont, "Silicon Implementation of SHA-3 Finalists: BLAKE, Grostl, JH, Keccak, Skein," Ecrypt II Hash Workshop 2011, Tallinn, Estonia, May 2011.

 

  • I. Kim, A. Maiti, L. Nazhandali, P. Schaumont, V. Vivekraja and H. Zhang, "From Statistics to Circuits: Foundations for Future Physical Unclonable Functions," Chapter 3 in "Towards Hardware Intrinsic Security: Foundations and Practice," Eds. Ahmad Sadeghi, David Naccache, 55-78, 2010, Springer. DOI: 10.1007/978-3-642-14452-3_3.

 

  • D. Ganta, V. Vivekraja, K. Priya, L. Nazhandali, "A Highly Stable Leakage-Based Silicon Physical Unclonable Function", 24th International Conference on VLSI Design (VLSI Design), Chennai, India, Jan 2011.

 

  • M. Henry, R. Lyerly, L Nazhandali, A. Fruehling, D. Peroulis, "MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing", 24th International Conference on VLSI Design (VLSI Design), Chennai, India, Jan 2011.

 

  • V. Vivekraja, L. Nazhandali, ″Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs″, 24th International Conference on VLSI Design (VLSI Design), Chennai, India, Jan 2011.

 

 

  • X. Guo, S. Huang, L. Nazhandali, P. Schaumont, "Fair and Comprehensive Performance Evaluation of 14 Second Round SHA-3 ASIC Implementations", NIST 2nd SHA-3 Candidate Conference, Santa Barbara, CA, August 2010.

 

  • K. Kobayashi, J. Ikegami, M. Knezevid, X. Guo, S. Matsuo, S. Huang, L. Nazhandali, U. Kocabas, J. Fan, A. Satoh, I. Verbauwhede, K. Sakiyama, K. Ota, "A Prototyping Platform for Performance Evaluation of SHA-3 Candidates", IEEE International Symposium on Hardware-Oriented Security and Trust (HOST2010) , June 2010.

 

  • Henry, M.B., Nazhandali, L., ″From Transistors to MEMS: Throughput Aware Power-Gating in CMOS Circuits,″ Design, Automation & Test in Europe Conference, 2010. DATE '10. , pp.130-136, Dresden, Germany, 8-12 March 2010.

 

  • Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Ann Reeves, Michael Minuth, Ryan Helfand, Todd Austin, Dennis Sylvester, David Blaauw, ″Energy Efficient Subthreshold Processor Design,″ IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Vol. 17, No. 8, August 2009, pgs. 1127 - 1137.

 

  • Vignesh Vivekraja, Leyla Nazhandali, ″Circuit-Level Techniques for Reliable Physically Uncloneable Functions″, IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2009), San Francisco, CA, USA, July 2009.

 

  • Bell, S. Raman, A. MacKenzie, P. Plassmann, C. Wyatt, L. DaSilva, L. Nazhandali, M. Agah, ″Increasing the Enrollment, Retention and Satisfaction of First-Year Students in Electrical Engineering, Computer Engineering, and Computer Science,″ ASEE Annual Conference, Austin, TX, June 14-17, 2009.

 

  • M.B. Henry, S. Griffin, and L. Nazhandali, ″Fast simulation framework for subthreshold circuits″, IEEE International Symposium on Circuits and Systems, Taipei, Taiwan, May 2009.

 

  • M. B. Henry and L. Nazhandali, Hybrid super/subthreshold design of a low power scalable-throughput FFT architecture, volume 5409 of Lecture Notes in Computer Science, pages 278-292, Springer Berlin / Heidelberg, 2009.

 

  • Michael Henry, Syed Imtiaz M Haider, Leyla Nazhandali, ″A Low-Power Parallel Implementation of Discrete Wavelet Transform using Subthreshold Voltage Technology″, Architecture and Synthesis for Embedded Systems (CASES), Atlanta, GA, October 2008.

 

  • Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, David Blaauw, ″Exploring Variability and Performance in a Sub-200 mV Processor″, IEEE Journal of Solid-State Circuits (JSSC), Invited Paper to the Special Issue on VLSI Circuits, Vol. 43, No. 4, April 2008, pgs. 881-891.

 

  • Syed Imtiaz M Haider, Leyla Nazhandali, ″Utilizing Sub-threshold Technology for the Creation of Secure Circuits,″ IEEE International Symposium on Circuits and Systems ISCAS, Seattle, Washington, USA, 18-21 May 2008.

 

  • Syed Imtiaz M Haider, Leyla Nazhandali, ″A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection,″ International Conference on Compilers, Architecture and Synthesis for Embedded Systems CASES, Salzburg, Austria, Sep. 30-Oct. 5, 2007.

 

  • Syed Imtiaz M Haider, Leyla Nazhandali, ″A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection″, International Conference on Compilers, Architecture and Synthesis for Embedded Systems CASES, Salzburg, Austria, Sep. 30-Oct. 5, 2007.

 

  • Scott Hanson, Bo Zhai, Mingoo Seok, Brian Cline, Kevin Zhou, Meghna Singhal, Michael Minuth, Javin Olson, Leyla Nazhandali, Todd Austin, Dennis Sylvester, David Blaauw, ″Performance and variability optimization strategies in a sub-200mV, 3.5pJ/inst, 11nW subthreshold processor,″ IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2007.

 

  • Bo Zhai, Leyla Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, David Blaauw, Todd Austin, ″A 2.60pJ/Inst. Subthreshold Sensor Processor for Optimal Energy Efficiency,″ IEEE Symposium on VLSI Circuits (VLSI-Symp), Honolulu, Hawaii USA, June 2006.

 

  • L. Nazhandali, M. Minuth, B. Zhai, and T. Austin, ″SenseBench: Toward an Accurate Evaluation of Sensor Network Processors″, 2005 IEEE International Symposium on Workload Characterization IISWC, Austin, Texas USA, October 6-8, 2005.

 

  • Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Scott Hanson, Todd Austin, David Blaauw, ″A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution,″ ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.

 

  • L. Nazhandali, B. Zhai, R. Helfand, M. Minuth, J. Olson, S. Pant, A. Reeves, T. Austin, and D. Blaauw, ″Energy Optimization of Subthreshold-Voltage Sensor Processors,″ The 32nd Annual International Symposium on Computer Architecture ISCA, Madison, Wisconsin USA, June 4-8, 2005.